US3971960A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop false output rejection circuit
Assignee: Motorola Solutions Inc
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Filing: 1975-03-05
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Granted: 1976-07-27
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Expires: 1995-03-05
Abstract
Abstract An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these "false" outputs eliminates their propagation in the digital system in which said flip-flop is employed.
Inventors
- 👤 Rodney J. Means
- 👤 Gene A. Schriber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:04
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
128 words
A digital logic circuit comprising: a. storage means having a first storage state and a second storage state for storing digital information; b. first input means coupled to said storage means and adapted to respond to a first input signal for causing said storage means to assume said first storage stage; c. second input means coupled to said storage means and adapted to respond to a second input signal for causing said storage means to assume said second storage state; and d. false output rejection circuit means coupled to the output of said storage means for generating a corrected replica of said first storage state when time asynchronism between said first input signal and said second input signal cause said storage means to assume a logically indeterminate state.
Claim 2
Dependent Claim
128 words
A digital logic circuit comprising: a. storage means having a first storage state and a second storage state for storing digital information; b. first input means coupled to said storage means and adapted to respond to a first input signal for causing said storage means to assume said first storage stage; c. second input means coupled to said storage means and adapted to respond to a second input signal for causing said storage means to assume said second storage state; and d. false output rejection circuit means coupled to the output of said storage means for generating a corrected replica of said first storage state when time asynchronism between said first input signal and said second input signal cause said storage means to assume a logically indeterminate state.
Claim 3
Dependent Claim
16 words
The circuit recited in claim 1 wherein said storage means is a cross-coupled coincident gate flip-flop.
Claim 4
Dependent Claim
14 words
The circuit recited in claim 2 wherein said first input means includes coincident gates.
Claim 5
Dependent Claim
18 words
The circuit recited in claim 3 wherein said false output rejection circuit means further comprises threshold detection circuits.
Claim 6
Dependent Claim
13 words
The circuit recited in claim 4 wherein said coincidence gates are NOR gates.
Claim 7
Dependent Claim
16 words
The circuit recited in claim 5 wherein said coincidence gates are made up of MOSFET devices.
Claim 8
Dependent Claim
14 words
The circuit recited in claim 6 wherein said threshold detection circuits are MOSFET inverters.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-27 | 1980-01-26 | 1980-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-27 | 1984-01-26 | 1984-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-27 | 1988-01-26 | 1988-07-27 | $7700.00 | Window Closed / Lapsed |