Set-preferring R-S flip-flop circuit

Claim 2

A set-preferring R-S flip-flop circuit comprising: a first inverter circuit which includes first, third and fifth transistors of the same first conductivity type, each having an input electrode, an output electrode and a control electrode, second, fourth and sixth transistors, of the same second conductivity type which is opposite to that of said first, third and fifth transistors, each having an input electrode, an output electrode, and a control electrode, said first and third transistors having their input and output electrodes connected in parallel, said fifth transistor being connected in series with said parallel-connected first and third transistors between a first power source terminal and a first output terminal; said sixth transistor being connected in series between said first output terminal and a second power source terminal; said second and fourth transistors being connected in series between said first output terminal and said second power source terminal; a second inverter circuit which includes a seventh transistor of said first conductivity type and an eighth transistor of said second conductivity type, each having an input electrode, an output electrode, and a control electrode; said seventh transistor being connected in series between a second output terminal and said first power source terminal; said eighth transistor being connected in series between said second output terminal and said second power source terminal; first means for coupling the output of said first inverter circuit to the control electrodes of said seventh and eighth transistors; second means for feeding-back the output of said second inverter circuit to the control electrodes of said first and second transistors; and third means for applying a reset input signal to the control electrodes of said third and fourth transistors and a set input signal to the control electrodes of said fifth and sixth transistors, so aS to make said flip-flop circuit have a function that when said fifth and sixth transistors are respectively non-conductive and conductive, said flip-flop circuit is in a set state irrespective of the reset input signal, and when said fifth and sixth transistors are respectively conductive and nonconductive, said flip-flop circuit remains in the previous state thereof or is in a reset state in accordance with the conductive or nonconductive state of said third and fourth transistors which operate complementarily.

Claim 3

A set-preferring R-S flip-flop circuit as defined in claim 1, wherein said first means comprises a delay means, so that the output of said second inverter circuit is delayed with respect to said set and reset signals.

Claim 4

A set-preferring R-S flip-flop circuit as defined in claim 2, wherein said delay means comprises a ninth transistor, the conduction of which is controlled by a first clock signal applied thereto.

Claim 5

A set-preferring R-S flip-flop circuit as defined in claim 3, wherein said ninth transistor has the first conductivity type and said delay means further comprises a tenth transistor of the second conductivity type which is connected to said ninth transistor in a parallel configuration and the conduction of which is controlled by the inverted signal of said first clock signal.

Claim 6

A set preferring R-S flip-flop circuit as defined in claim 4, further comprising an eleventh and a twelfth transistor each having the first and the second conductivity type, respectively, said eleventh transistor being connected in series with said fifth transistor between the first power source terminal and said first output terminal and said twelfth transistor being connected in series with said fourth and sixth transistors between the second power source terminal and said first output terminal, and means for applying a clock signal and its inverted clock signal to said eleventh and twelfth transistors, respectively, so as to control the conduction thereof.

Claim 7

In a flip-flop circuit which comprises first, third and fifth transistors of a first conductivity type, each having an input electrode, an output electrode, and a control electrode; second, fourth and sixth transistors, of a second conductivity type, opposite said first conductivity type, each having an input electrode, an output electrode, and a control electrode; said first and third transistors having their input and output electrodes connected in parallel; said fifth transistor having its input and output electrodes connected in series with said parallel connected first and third transistors between a first power source terminal and a first output terminal; said second and fourth transistors being connected in series between said first output terminal and a second power source terminal; said sixth transistor having its control electrode connected to the control electrode of said fifth transistor; a seventh transistor of said first conductivity type and an eighth transistor of said second conductivity type, each having an input electrode, an output electrode, and a control electrode; said seventh transistor being connected in series between a second output terminal and said first power source terminal; said eighth transistor being connected in series between said second output terminal and said second power source terminal; first means for coupling said first output terminal to the control electrodes of said seventh and eighth transistors; and second means for coupling said second output terminal to the control electrodes of said first and second transistors; the improvement wherein said flip-flop is further interconnected and controlled to operate as a set-preferring R-S flip-flop wherein the input and output electrodes of said sixth transistor are connected to the output electrodes of said first and second transistors and to the input electrode of said fourth transistor, respectively; a RESET input signal is applied to the control electrodes of said third and fourth transistors, and a SET input signal is applied to the control electrodes of said fifth and sixth transistors; and wherein, upon said fifth and sixth transistors being rendered respectively non-conductive and conductive, said flip-flop circuit is in the SET state irrespective of said RESET input signal, and upon said fifth and sixth transistors being rendered respectively conductive and non-conductive, said flip-flop circuit remains in its previous state or is reset in accordance with the conductive or non-conductive state of said third and fourth transistors which operate complementarily.

Claim 8

In a flip-flop circuit which comprises first, third and fifth transistors of a first conductivity type, each having an input electrode, an output electrode, and a control electrode; second, fourth and sixth transistors, of a second conductivity type, opposite said first conductivity type, each having an input electrode, an output electrode, and a control electrode; said first and third transistors having their input and output electrodes connected in parallel; said fifth transistor having its input and output electrodes connected in series with said parallel connected first and third transistors between a first power source terminal and a first output terminal; said second and fourth transistors being connected in series between said first output terminal and a second power source terminal; said sixth transistor having its control electrode connected to the control electrode of said fifth transistor; a seventh transistor of said first conductivity type and an eighth transistor of said second conductivity type, each having an input electrode, an output electrode, and a control electrode; said seventh transistor being connected in series between a second output terminal and said first power source terminal; said eighth transistor being connected in series between said second output terminal and said second power source terminal; first means for coupling said first output terminal to the control electrodes of said seventh and eighth transistors; and second means for coupling said second output terminal to the control electrodes of said first and second transistors; the improvement wherein said flip-flop is further interconnected and controlled to operate as a set-preferring R-S flip-flop wherein the input and output electrodes of said sixth transistor are connected to the output electrodes of said first and second transistors and to the input electrode of said fourth transistor, respectively; a RESET input signal is applied to the control electrodes of said third and fourth transistors, and a SET input signal is applied to the control electrodes of said fifth and sixth transistors; and wherein, upon said fifth and sixth transistors being rendered respectively non-conductive and conductive, said flip-flop circuit is in the SET state irrespective of said RESET input signal, and upon said fifth and sixth transistors being rendered respectively conductive and non-conductive, said flip-flop circuit remains in its previous state or is reset in accordance with the conductive or non-conductive state of said third and fourth transistors which operate complementarily.

Claim 9

The improvement according to claim 6, wherein said first means includes a delay circuit, so that the output at said second output terminal is delayed with respect to said SET and RESET signals.

Claim 10

The improvement according to claim 7, wherein said delay circuit comprises a ninth transistor, the conduction of which is controlled by a first clock signal applied thereto.

Claim 11

The improvement according to claim 8, wherein said ninth transistor is of the first conductivity type and said delay circuit further comprises a tenth transistor of the second conductivity type, connected to said ninth transistor in a parallel configuration, the conduction of said tenth transistor being controlled by the inverted signal of said first clock signal.

Claim 12

The improvement according to claim 9, further including an eleventh transistor of the first conductivity type and a twelfth transistor of the second conductivity type, said eleventh transistor being connected in series with said fifth transistor between the first power source terminal and said first output terminal, and said twelfth transistor being connected in series with said fourth and sixth transistors between said second power source terminal and said first output terminal, and means for applying a clock signal and its inverted clock signal into said eleventh and twelfth transistors, respectively, so as to control the conduction thereof.