Bidirectional data line driver circuit for a mosfet memory

Claim 2

An electrical signal translation circuit utilizing electronic switch means having a current control terminal and a first and a second current conducting terminal and powered by at least one supply potential, comprising in combination: an input and an output terminal; first and second electronic switch means having respective first and second current conducting terminals connected in parallel and additionally including circuit means coupling said first current conducting terminals to said supply potential, and circuit means coupling the current control terminal of said first electronic switch means to said input terminal; third and fourth electronic switch means having respective first and second current conducting terminals connected in series between a point of reference potential and said second current conducting terminals of said first and second electronic switch means, and additionally including circuit means coupling the current control terminal of said third semiconductor switch means to the current control terminal of said second electronic switch means and circuit means coupling the current control terminal of said fourth electronic switch means to said input terminal; fifth, sixth and seventh electronic switch means coupled together in series by their respective first and second current conducting terminals between said point of reference potential and said supply potential, said fifth and sixth electronic switch means having a common connection between respective second and first current conducting terminals and additionally including circuit means coupling said common connection to said output terminal, circuit means coupling the current control terminal of said fifth electronic switch means and the control terminal of said seventh electronic switch means commonly connected to said common connection of the second current conducting terminals of said first and second electronic switch means; and a control input terminal commonly connected to the current control terminals of said second, third and sixth electronic switch means being adapted to provide a control signal for enabling an inhibiting signal flow from said input terminal to said output terminal.

Claim 3

The invention as defined by claim 1 wherein all said electronic switch means comprise semiconductor switch means.

Claim 4

The invention as defined by claim 2 wherein said semiconductor switch means comprise transistors.

Claim 5

The invention as defined by claim 3 wherein said transistors comprise insuLated gate field effect transistors.

Claim 6

the invention as defined by claim 1 wherein said first, second and fifth electronic switch means comprise P-channel metal oxide semiconductor field effect transistors and said third, fourth, sixth and seventh electronic switch means comprise N-channel metal oxide semiconductor field effect transistors.

Claim 7

A data line driver circuit for an integrated circuit memory coupled between an external input/output data line and an internal input/output data line connected to at least one memory cell and powered by at least one supply potential, comprising in combination: a first and a second circuit section, each said section having an input terminal and an output terminal and including circuit means commonly connecting the input terminal of said first circuit section and the output terminal of said second circuit section to said external input/output data line and the output terminal of said first circuit section and the input terminal of said second circuit section to said internal input/output data lines, each said section utilizing semiconductor switches having a control terminal and a first and a second current conducting terminal and comprising; first and second parallely connected semiconductor switches including circuit means commonly connecting the respective first current conducting terminals to said supply potential and the respective second current conducting terminals at a common junction and circuit means coupling the control terminal of said first semiconductor switch to said input terminal; a third and fourth semiconductor switch including circuit means connecting said first current conducting terminal of said third semiconductor switch to the second current conducting terminal of said fourth semiconductor switch, circuit means connecting the second current conducting terminal of said third semiconductor switch to said common junction, circuit means connecting the first current conducting terminal of said fourth semiconductor switch to a point of reference potential, and circuit means connecting the control terminal of said fourth semiconductor switch to said input terminal; a fifth semiconductor switch including circuit means connecting said first current conducting terminal to said supply potential, circuit means connecting said control terminal to said common junction and circuit means connecting said second current conducting terminal to said output terminal; a sixth semiconductor switch including circuit means coupling said second current conducting terminal to said second current conducting terminal of said fifth semiconductor switch and circuit means connecting said control terminal commonly to the control terminals of said second and third semiconductor switches; a seventh semiconductor switch including circuit means coupling said second current conducting terminal to the first current conducting terminal of said sixth semiconductor switch, circuit means connecting the first current conducting terminal to said point of reference potential and circuit means connecting said control terminal to said common junction of said first and second semiconductor switch; and a control input terminal including circuit means commonly connecting said control input terminal to the control terminals of said third, fourth and sixth semiconductor switches, said first and second circuit sections being adapted to be selectively enabled and inhibited by a binary signal applied thereto whereby binary data is translated from said external input/output data line to said internal input/output data line by means of said first circuit section and binary data is transferred from said internal input/output data line to said external input/output data line through said second circuit section.

Claim 8

A data line driver circuit for an integrated circuit memory coupled between an external input/output data line and an internal input/output data line connected to at least one memory cell and powered by at least one supply potential, comprising in combination: a first and a second circuit section, each said section having an input terminal and an output terminal and including circuit means commonly connecting the input terminal of said first circuit section and the output terminal of said second circuit section to said external input/output data line and the output terminal of said first circuit section and the input terminal of said second circuit section to said internal input/output data lines, each said section utilizing semiconductor switches having a control terminal and a first and a second current conducting terminal and comprising; first and second parallely connected semiconductor switches including circuit means commonly connecting the respective first current conducting terminals to said supply potential and the respective second current conducting terminals at a common junction and circuit means coupling the control terminal of said first semiconductor switch to said input terminal; a third and fourth semiconductor switch including circuit means connecting said first current conducting terminal of said third semiconductor switch to the second current conducting terminal of said fourth semiconductor switch, circuit means connecting the second current conducting terminal of said third semiconductor switch to said common junction, circuit means connecting the first current conducting terminal of said fourth semiconductor switch to a point of reference potential, and circuit means connecting the control terminal of said fourth semiconductor switch to said input terminal; a fifth semiconductor switch including circuit means connecting said first current conducting terminal to said supply potential, circuit means connecting said control terminal to said common junction and circuit means connecting said second current conducting terminal to said output terminal; a sixth semiconductor switch including circuit means coupling said second current conducting terminal to said second current conducting terminal of said fifth semiconductor switch and circuit means connecting said control terminal commonly to the control terminals of said second and third semiconductor switches; a seventh semiconductor switch including circuit means coupling said second current conducting terminal to the first current conducting terminal of said sixth semiconductor switch, circuit means connecting the first current conducting terminal to said point of reference potential and circuit means connecting said control terminal to said common junction of said first and second semiconductor switch; and a control input terminal including circuit means commonly connecting said control input terminal to the control terminals of said third, fourth and sixth semiconductor switches, said first and second circuit sections being adapted to be selectively enabled and inhibited by a binary signal applied thereto whereby binary data is translated from said external input/output data line to said internal input/output data line by means of said first circuit section and binary data is transferred from said internal input/output data line to said external input/output data line through said second circuit section.

Claim 9

The invention as defined by claim 6 wherein all said semiconductor switches are comprised of transistors.

Claim 10

The invention as defined by claim 6 wherein said first, second and fifth semiconductor switches are comprised oF field effect transistors of a first semiconductivity type and said third, fourth, sixth and seventh semiconductor switches are comprised of field effect transistors of a second semiconductivity type

Claim 11

The invention as defined by claim 6 wherein all said semiconductor switches are comprised of field effect transistors.

Claim 12

The invention as defined by claim 6 wherein said first, second, and fifth semiconductor switches are comprised of insulated gate field effect transistors of a first conductivity type and said third, fourth, sixth and seventh semiconductor switches are comprised of insulated gate field effect transistors of a second conductivity type.

Claim 13

The invention as defined by claim 6 wherein said first, second and fourth semiconductor switches are comprised of P-channel metal oxide field effect transistors and said third fourth, sixth and seventh semiconductor switches are comprised of N-channel metal oxide field effect transistors.