US3753009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Resettable binary flip-flop of the semiconductor type
Assignee: Motorola Solutions Inc
•
Filing: 1971-08-23
•
Granted: 1973-08-14
•
Expires: 1991-08-23
Abstract
Abstract A bistable flip-flop circuit utilizing insulated gate field effect transistors in a plurality of AND, NOR and inverter circuits connected to receive a signal and the inverse thereof on two inputs and to supply an output signal and the inverse thereof on two outputs, the outputs being resettable to specific levels upon the application of a reset signal to a reset input.
Inventors
- 👤 S Clapper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 110
Claim 1
Independent Claim
423 words
In a resettable binary flip-flop of the semiconductor type having first, second, third and fourth AND gate circuits each having a plurality of inputs and an output, first and second NOR gate circuits each having a plurality of inputs and an output, the outputs of said first and second AND gate circuits being connected to two inputs of said first NOR gate circuit and the outputs of said third and fourth AND gate circuits being connected to two inputs of said second NOR gate circuit, and first and second inverter circuits each having an input and an output, the oUtput of said first NOR gate circuit being connected to the input of said first inverter circuit and to an input of said third AND gate circuit, the output of said second NOR gate circuit being connected to the input of said second inverter circuit, the output of said first inverter being connected to an input of said first AND gate circuit and the output of said second inverter circuit being connected to an input of said second AND gate circuit and an input of said fourth AND gate circuit, an input of each of said second and fourth AND gate circuits being connected together for receiving an input signal thereon and an input of each of said first and third AND gate circuits being connected together for receiving a signal which is the inverse of the input signal thereon, the improvement comprising: a. an input of each of said first, second and fourth AND gate circuits being connected together for receiving a reset signal thereon, b. said first and second AND gate circuits and said connected first NOR gate circuit including a plurality of field effect transistors connected in parallel therein and a plurality of field effect transistors connected in series therein and further connected for receiving the reset signals on the gate of at least one of said parallel and one of said series transistors; and c. said third and fourth AND gate circuits and the connected second NOR gate circuit including a plurality of field effect transistors connected in parallel therein and a plurality of field effect transistors connected in series therein and further connected for receiving the reset signal on the gate of at least one of said parallel and one of said series transistors, said additional semiconductor devices serving to reset the flip-flop to a predetermined output condition and to prevent operation of the flip-flop, regardless of the signals present at the inputs of the various circuits during reset.
Claim 2
Dependent Claim
423 words
In a resettable binary flip-flop of the semiconductor type having first, second, third and fourth AND gate circuits each having a plurality of inputs and an output, first and second NOR gate circuits each having a plurality of inputs and an output, the outputs of said first and second AND gate circuits being connected to two inputs of said first NOR gate circuit and the outputs of said third and fourth AND gate circuits being connected to two inputs of said second NOR gate circuit, and first and second inverter circuits each having an input and an output, the oUtput of said first NOR gate circuit being connected to the input of said first inverter circuit and to an input of said third AND gate circuit, the output of said second NOR gate circuit being connected to the input of said second inverter circuit, the output of said first inverter being connected to an input of said first AND gate circuit and the output of said second inverter circuit being connected to an input of said second AND gate circuit and an input of said fourth AND gate circuit, an input of each of said second and fourth AND gate circuits being connected together for receiving an input signal thereon and an input of each of said first and third AND gate circuits being connected together for receiving a signal which is the inverse of the input signal thereon, the improvement comprising: a. an input of each of said first, second and fourth AND gate circuits being connected together for receiving a reset signal thereon, b. said first and second AND gate circuits and said connected first NOR gate circuit including a plurality of field effect transistors connected in parallel therein and a plurality of field effect transistors connected in series therein and further connected for receiving the reset signals on the gate of at least one of said parallel and one of said series transistors; and c. said third and fourth AND gate circuits and the connected second NOR gate circuit including a plurality of field effect transistors connected in parallel therein and a plurality of field effect transistors connected in series therein and further connected for receiving the reset signal on the gate of at least one of said parallel and one of said series transistors, said additional semiconductor devices serving to reset the flip-flop to a predetermined output condition and to prevent operation of the flip-flop, regardless of the signals present at the inputs of the various circuits during reset.
Claim 3
Dependent Claim
106 words
A resettable binary flip-flop of the semiconductor type comprising: a. first, second, third and fourth AND gate circuits each having a plurality of inputs and an output; b. first and second NOR gate circuits each having a plurality of inputs and an output, the outputs of said first and second AND gate circuits being connected to two inputs of said first NOR gate circuit and the outputs of said third and fourth AND gate circuits being connected to two inputs of said second NOR gate circuit; c. said first and second AND gate circuits and said first NOR gate circuit forming a first logic circuit including
Claim 4
Dependent Claim
106 words
A resettable binary flip-flop of the semiconductor type comprising: a. first, second, third and fourth AND gate circuits each having a plurality of inputs and an output; b. first and second NOR gate circuits each having a plurality of inputs and an output, the outputs of said first and second AND gate circuits being connected to two inputs of said first NOR gate circuit and the outputs of said third and fourth AND gate circuits being connected to two inputs of said second NOR gate circuit; c. said first and second AND gate circuits and said first NOR gate circuit forming a first logic circuit including
Claim 5
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal,
Claim 6
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal,
Claim 7
Dependent Claim
31 words
first, second and third P-channel transistors being connected in parallel, with the sources adapted to be connected to a positive source of voltage and the drains connected to a first terminal;
Claim 8
Dependent Claim
31 words
first, second and third P-channel transistors being connected in parallel, with the sources adapted to be connected to a positive source of voltage and the drains connected to a first terminal;
Claim 9
Dependent Claim
31 words
first, second and third P-channel transistors being connected in parallel, with the sources adapted to be connected to a positive source of voltage and the drains connected to a first terminal;
Claim 10
Dependent Claim
31 words
first, second and third P-channel transistors being connected in parallel, with the sources adapted to be connected to a positive source of voltage and the drains connected to a first terminal;
Claim 11
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal;
Claim 12
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal;
Claim 13
Dependent Claim
31 words
first, second and third P-channel transistors being connected in parallel, with the sources adapted to be connected to a positive source of voltage and the drains connected to a first terminal;
Claim 14
Dependent Claim
31 words
first, second and third P-channel transistors being connected in parallel, with the sources adapted to be connected to a positive source of voltage and the drains connected to a first terminal;
Claim 15
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal;
Claim 16
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal;
Claim 17
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal,
Claim 18
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between a line adapted to be connected to a source of voltage and a first terminal,
Claim 19
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between A line adapted to be connected to a source of voltage and a first terminal;
Claim 20
Dependent Claim
31 words
first, second and third semiconductor means being connected with the sources and drains in parallel between A line adapted to be connected to a source of voltage and a first terminal;
Claim 21
Dependent Claim
22 words
fourth and fifth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal,
Claim 22
Dependent Claim
22 words
fourth and fifth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal,
Claim 23
Dependent Claim
22 words
fourth and fifth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal;
Claim 24
Dependent Claim
22 words
fourth and fifth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal;
Claim 25
Dependent Claim
30 words
A resettable binary flip-flop as set forth in claim 2 wherein the third and fourth AND gate circuits and the second NOR gate circuit comprise a second logic circuit including
Claim 26
Dependent Claim
22 words
fourth and fifth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal;
Claim 27
Dependent Claim
22 words
fourth and fifth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal;
Claim 28
Dependent Claim
26 words
fourth, fifth and sixth P-channel transistors being connected in parallel with the sources connected to said first terminal and the drains connected to a second terminal;
Claim 29
Dependent Claim
26 words
fourth, fifth and sixth P-channel transistors being connected in parallel with the sources connected to said first terminal and the drains connected to a second terminal;
Claim 30
Dependent Claim
23 words
fourth, fifth and sixth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal;
Claim 31
Dependent Claim
23 words
fourth, fifth and sixth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal;
Claim 32
Dependent Claim
25 words
fourth and fifth P-channel transistors being connected in parallel, with the sources connected to said first terminal and the drains connected to a second terminal;
Claim 33
Dependent Claim
25 words
fourth and fifth P-channel transistors being connected in parallel, with the sources connected to said first terminal and the drains connected to a second terminal;
Claim 34
Dependent Claim
25 words
fourth and fifth P-channel transistors being connected in parallel, with the sources connected to said first terminal and the drains connected to a second terminal;
Claim 35
Dependent Claim
25 words
fourth and fifth P-channel transistors being connected in parallel, with the sources connected to said first terminal and the drains connected to a second terminal;
Claim 36
Dependent Claim
23 words
fourth, fifth and sixth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal,
Claim 37
Dependent Claim
23 words
fourth, fifth and sixth semiconductor means being connected with the sources and drains in parallel between said first terminal and a second terminal,
Claim 38
Dependent Claim
23 words
seventh, eighth and ninth semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 39
Dependent Claim
23 words
seventh, eighth and ninth semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 40
Dependent Claim
18 words
first, second and third N-channel transistors being connected in series between said second terminal and a common line;
Claim 41
Dependent Claim
18 words
first, second and third N-channel transistors being connected in series between said second terminal and a common line;
Claim 42
Dependent Claim
18 words
first, second and third N-channel transistors being connected in series between said second terminal and a common line;
Claim 43
Dependent Claim
18 words
first, second and third N-channel transistors being connected in series between said second terminal and a common line;
Claim 44
Dependent Claim
23 words
seventh, eighth and ninth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 45
Dependent Claim
23 words
seventh, eighth and ninth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 46
Dependent Claim
23 words
sixth, seventh and eighth semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 47
Dependent Claim
23 words
sixth, seventh and eighth semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 48
Dependent Claim
18 words
first, second and third N-channel transistors being connected in series between said second terminal and a common line;
Claim 49
Dependent Claim
18 words
first, second and third N-channel transistors being connected in series between said second terminal and a common line;
Claim 50
Dependent Claim
83 words
A resettable binary flip-flop as set forth in claim 3 wherein three transistors are utilized to provide the dual functions of the first, second and third semiconductor means in the first and the second logic circuits; three transistors are utilized to provide the dual functions of the eighth, ninth and 12th semiconductor means of the first logic circuit and the seventh, eighth and 10th semiconductor means of the second logic circuit; and the remaining semiconductor means are transistors each performing a single function.
Claim 51
Dependent Claim
23 words
sixth, seventh and eighth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 52
Dependent Claim
23 words
sixth, seventh and eighth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 53
Dependent Claim
23 words
sixth, seventh and eighth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 54
Dependent Claim
23 words
sixth, seventh and eighth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 55
Dependent Claim
22 words
ninth and tenth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 56
Dependent Claim
22 words
ninth and tenth semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 57
Dependent Claim
23 words
tenth, 11th and 12th semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 58
Dependent Claim
23 words
tenth, 11th and 12th semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 59
Dependent Claim
22 words
ninth and 10th semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 60
Dependent Claim
22 words
ninth and 10th semiconductor means being connected with the sources and drains in series between said second terminal and a common line;
Claim 61
Dependent Claim
17 words
A resettable binary flip-flop as set forth in claim 4 wherein the transistors are field effect transistors.
Claim 62
Dependent Claim
18 words
fourth, fifth and sixth N-channel transistors being connected in series between said second terminal and the common line;
Claim 63
Dependent Claim
18 words
fourth, fifth and sixth N-channel transistors being connected in series between said second terminal and the common line;
Claim 64
Dependent Claim
22 words
ninth and tenth semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 65
Dependent Claim
22 words
ninth and tenth semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 66
Dependent Claim
17 words
fourth and fifth N-channel transistors being connected in series between said second terminal and the common line;
Claim 67
Dependent Claim
17 words
fourth and fifth N-channel transistors being connected in series between said second terminal and the common line;
Claim 68
Dependent Claim
17 words
fourth and fifth N-channel transistors being connected in series between said second terminal and the common line;
Claim 69
Dependent Claim
17 words
fourth and fifth N-channel transistors being connected in series between said second terminal and the common line;
Claim 70
Dependent Claim
23 words
tenth, 11th and 12th semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 71
Dependent Claim
23 words
tenth, 11th and 12th semiconductor means being connected with the sources and drains in series between said second terminal and a common line,
Claim 72
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said seventh, eighth and ninth semiconductor means, and
Claim 73
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said seventh, eighth and ninth semiconductor means, and
Claim 74
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said sixth, seventh and eighth semiconductor means; and
Claim 75
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said sixth, seventh and eighth semiconductor means; and
Claim 76
Dependent Claim
28 words
the gates of said first, second and third P-channel transistors being connected one each to one of the gates of said first, second and third N-channel transistors; and
Claim 77
Dependent Claim
28 words
the gates of said first, second and third P-channel transistors being connected one each to one of the gates of said first, second and third N-channel transistors; and
Claim 78
Dependent Claim
28 words
the gates of said first, second and third P-channel transistors being connected one each to one of the gates of said first, second and third N-channel transistors; and
Claim 79
Dependent Claim
28 words
the gates of said first, second and third P-channel transistors being connected one each to one of the gates of said first, second and third N-channel transistors; and
Claim 80
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said sixth, seventh and eighth semiconductor means, and
Claim 81
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said sixth, seventh and eighth semiconductor means, and
Claim 82
Dependent Claim
28 words
the gates of said first, second and third P-channel transistors being connected one each to one of the gates of said first, second and third N-channel transistors; and
Claim 83
Dependent Claim
28 words
the gates of said first, second and third P-channel transistors being connected one each to one of the gates of said first, second and third N-channel transistors; and
Claim 84
Dependent Claim
16 words
a resettable binary flip-flop as set forth in claim 2 wherein the 12 semiconductor means include
Claim 85
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said sixth, seventh and eighth semiconductor means; and
Claim 86
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said sixth, seventh and eighth semiconductor means; and
Claim 87
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said seventh, eighth and ninth semiconductor means; and
Claim 88
Dependent Claim
28 words
the gates of said first, second and third semiconductor means being connected one each to one of the gates of said seventh, eighth and ninth semiconductor means; and
Claim 89
Dependent Claim
33 words
the gates of said fourth, fifth and sixth semiconductor means being connected one each to one of the gates of said 10th, 11th and 12th semiconductor means; b. a second logic circuit including
Claim 90
Dependent Claim
33 words
the gates of said fourth, fifth and sixth semiconductor means being connected one each to one of the gates of said 10th, 11th and 12th semiconductor means; b. a second logic circuit including
Claim 91
Dependent Claim
205 words
the gates of said fourth, fifth and sixth semiconductor means being connected one each to one of the gates of said 10th, 11th and 12th semiconductor means; d. first and second inverter circuits each having an input and an output, the output of said first NOR gate circuit being connected to the input of said first inverter circuit, and to an input of said third AND gate circuit the output of said second NOR gate circuit Being connected to the input of said second inverter circuit, the output of said first inverter being connected to an input of said first AND gate circuit, and the output of said second inverter circuit being connected to an input of said second AND gate circuit and an input of said fourth AND gate circuit; and e. an input of each of said first, second and fourth AND gate circuits being connected together for receiving a reset signal thereon, an input of each of said second and fourth AND gate circuits being connected together for receiving an input signal thereon, and an input of each of said first and third AND gate circuits being connected together for receiving a signal which is the inverse of the input signal thereon.
Claim 92
Dependent Claim
205 words
the gates of said fourth, fifth and sixth semiconductor means being connected one each to one of the gates of said 10th, 11th and 12th semiconductor means; d. first and second inverter circuits each having an input and an output, the output of said first NOR gate circuit being connected to the input of said first inverter circuit, and to an input of said third AND gate circuit the output of said second NOR gate circuit Being connected to the input of said second inverter circuit, the output of said first inverter being connected to an input of said first AND gate circuit, and the output of said second inverter circuit being connected to an input of said second AND gate circuit and an input of said fourth AND gate circuit; and e. an input of each of said first, second and fourth AND gate circuits being connected together for receiving a reset signal thereon, an input of each of said second and fourth AND gate circuits being connected together for receiving an input signal thereon, and an input of each of said first and third AND gate circuits being connected together for receiving a signal which is the inverse of the input signal thereon.
Claim 93
Dependent Claim
234 words
the gates of said fourth and fifth semiconductor means being connected one each to one of the gates of said ninth and 10th semiconductor means; c. first and second inverter circuits each having an input and an output, the second terminal of said first logic circuit being connected to the input of said first inverter circuit, and to the gate of the fourth semiconductor means of said second logic circuit, the second terminal of said second logic circuit being connected to the input of said second inverter circuit, the output of said first inverter circuit being connected to the gate of the fourth semiconductor means of said first logic circuit, and the output of said second inverter circuit being connected to the gates of the third semiconductor means of each of said first and second logic circuits; and d. the gates of the second semiconductor means of each of the first and second logic circuits being connected to receive an input signal, the gates of the sixth semiconductor means of the first logic circuit and the fifth semiconductor means of the second logic circuit being connected to receive a signal which is the inverse of the input signal, and the gates of the first, fifth and ninth semiconductor means of the first logic circuit and the first and eighth semiconductor means of the second logic circuit being connected to receive a reset signal thereon.
Claim 94
Dependent Claim
234 words
the gates of said fourth and fifth semiconductor means being connected one each to one of the gates of said ninth and 10th semiconductor means; c. first and second inverter circuits each having an input and an output, the second terminal of said first logic circuit being connected to the input of said first inverter circuit, and to the gate of the fourth semiconductor means of said second logic circuit, the second terminal of said second logic circuit being connected to the input of said second inverter circuit, the output of said first inverter circuit being connected to the gate of the fourth semiconductor means of said first logic circuit, and the output of said second inverter circuit being connected to the gates of the third semiconductor means of each of said first and second logic circuits; and d. the gates of the second semiconductor means of each of the first and second logic circuits being connected to receive an input signal, the gates of the sixth semiconductor means of the first logic circuit and the fifth semiconductor means of the second logic circuit being connected to receive a signal which is the inverse of the input signal, and the gates of the first, fifth and ninth semiconductor means of the first logic circuit and the first and eighth semiconductor means of the second logic circuit being connected to receive a reset signal thereon.
Claim 95
Dependent Claim
25 words
the gates of said fourth and fifth semiconductor means being connected one each to one of the gates of said ninth and 10th semiconductor means.
Claim 96
Dependent Claim
25 words
the gates of said fourth and fifth semiconductor means being connected one each to one of the gates of said ninth and 10th semiconductor means.
Claim 97
Dependent Claim
203 words
the gates of said fourth and fifth semiconductor means being connected one each to one of the gates of said ninth and 10th semiconductor means; d. first and second inverter circuits each having an input and an output, the output of said first NOR gate circuit being connected to the input of said First inverter circuit, and to an input of said third AND gate circuit the output of said second NOR gate circuit being connected to the input of said second inverter circuit, the output of said first inverter being connected to an input of said first AND gate circuit, and the output of said second inverter circuit being connected to an input of said second AND gate circuit and an input of said fourth AND gate circuit; and e. an input of each of said first, second and fourth AND gate circuits being connected together for receiving a reset signal thereon, an input of each of said second and fourth AND gate circuits being connected together for receiving an input signal thereon, and an input of each of said first and third AND gate circuits being connected together for receiving a signal which is the inverse of the input signal thereon.
Claim 98
Dependent Claim
203 words
the gates of said fourth and fifth semiconductor means being connected one each to one of the gates of said ninth and 10th semiconductor means; d. first and second inverter circuits each having an input and an output, the output of said first NOR gate circuit being connected to the input of said First inverter circuit, and to an input of said third AND gate circuit the output of said second NOR gate circuit being connected to the input of said second inverter circuit, the output of said first inverter being connected to an input of said first AND gate circuit, and the output of said second inverter circuit being connected to an input of said second AND gate circuit and an input of said fourth AND gate circuit; and e. an input of each of said first, second and fourth AND gate circuits being connected together for receiving a reset signal thereon, an input of each of said second and fourth AND gate circuits being connected together for receiving an input signal thereon, and an input of each of said first and third AND gate circuits being connected together for receiving a signal which is the inverse of the input signal thereon.
Claim 99
Dependent Claim
16 words
A resettable binary flip-flop as set forth in claim 2 wherein the 10 semiconductor means include
Claim 100
Dependent Claim
27 words
the gates of said fourth, fifth and sixth P-channel transistors being connected one each to one of the gates of said fourth, fifth and sixth N-channel transistors.
Claim 101
Dependent Claim
27 words
the gates of said fourth, fifth and sixth P-channel transistors being connected one each to one of the gates of said fourth, fifth and sixth N-channel transistors.
Claim 102
Dependent Claim
25 words
the gates of said fourth and fifth P-channel transistors being connected one each to one of the gates of said fourth and fifth N-channel transistors.
Claim 103
Dependent Claim
25 words
the gates of said fourth and fifth P-channel transistors being connected one each to one of the gates of said fourth and fifth N-channel transistors.
Claim 104
Dependent Claim
25 words
the gates of said fourth and fifth P-channel transistors being connected one each to one of the gates of said fourth and fifth N-channel transistors.
Claim 105
Dependent Claim
25 words
the gates of said fourth and fifth P-channel transistors being connected one each to one of the gates of said fourth and fifth N-channel transistors.
Claim 106
Dependent Claim
30 words
A resettable binary flip-flop as set forth in claim 6 wherein the third and fourth AND gate circuits and the second NOR gate circuit comprise a second logic circuit including
Claim 107
Dependent Claim
15 words
A resettable binary flip-flop of the semiconductor type comprising: a. a first logic circuit including
Claim 108
Dependent Claim
15 words
A resettable binary flip-flop of the semiconductor type comprising: a. a first logic circuit including
Claim 109
Dependent Claim
106 words
A resettable binary flip-flop of the semiconductor type comprising: a. first, second, third and fourth AND gate circuits each having a plurality of inputs and an output; b. first and second NOR gate circuits each having a plurality of inputs and an output, the outputs of said first and second AND gate circuits being connected to two inputs of said first NOR gate circuit and the outputs of said third and fourth AND gate circuits being connected to two inputs of said second NOR gate circuit; c. said third and fourth AND gate circuits and said second NOR gate circuit forming a second logic circuit including
Claim 110
Dependent Claim
106 words
A resettable binary flip-flop of the semiconductor type comprising: a. first, second, third and fourth AND gate circuits each having a plurality of inputs and an output; b. first and second NOR gate circuits each having a plurality of inputs and an output, the outputs of said first and second AND gate circuits being connected to two inputs of said first NOR gate circuit and the outputs of said third and fourth AND gate circuits being connected to two inputs of said second NOR gate circuit; c. said third and fourth AND gate circuits and said second NOR gate circuit forming a second logic circuit including
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |