Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop

Claim 1

A phase and frequency compensation network for use in a multiple frequency digital phase-locked loop for effecting frequency adjustments in response to a programmable input signal by selectively summing or subtracting first and second clock signals' at a rate defined by a derived clock signal, said phase and frequency compensation network comprising: (a) first inverter means having an input coupled to said programmable input signal indicating positive or negative frequency adjustments; (b) first NAND gate means having first and second inputs and an output, said first input coupled to said derived clock signal and said second input coupled to said programmable input signal; (c) second NAND gate means having first and second inputs and an output, said first input coupled to said derived clock signal and said second input coupled to the output of said first inverter means; (d) first AND gate means having first and second inputs, and an output said first input coupled to the output of said second NAND gate means and said second input providing an input, wherein said input indicates a positive phase adjustment; (e) second inverter means having an input and an output, said input coupled to the output of said first NAND gate means; (f) third inverter means having an input and an output, said input coupled to the output of said second NAND gate means; (g) first flip-flop means having delay and clock inputs and a non-inverting ourput, said delay input coupled to the output of said second inverter means and said clock input coupled to said second clock signal; (h) second flip-flop means having delay and clock inputs and a non-inverting output, said delay input coupled to the output of said third inverter means and said clock coupled to said first clock signal; (i) third flip-flop means having delay and clock inputs and a non-inverting output said delay input coupled to the output of said first AND gate means and said clock coupled to said first clock signal; (j) second AND gate means having first and second inputs and an output, said first input coupled to the output of said first NAND gate and said second input providing an input wherein said input indicates a negative phase adjustment; (k) fourth flip-flop means having delay and clock inputs and a non-inverting output, said delay input coupled to the output of said second AND gate and said clock input coupled to said second clock signal; (l) NOR gate means having first and second inputs and an output, said first input coupled to the output of said second flip-flop means and said second input coupled to the output of said third flip-flop means; (m) first OR gate means having first and second inputs and an output, said first input coupled to the output of said first flip-flop means and said second input coupled to the output of said fourth flip-flop means; (n) third NAND gate means having first and second inputs and an output, said first input coupled to said second clock signal and said second input coupled to the output of said NOR gate means; (o) fourth NAND gate means having first and second inputs and an output, said first input coupled to said first clock signal and said second input coupled to the output of said first OR gate means; and (p) fifth NAND gate means having first and second inputs and an output, said first input coupled to the output of said third NAND gate means and second input coupled to the output of said fourth NAND gate means and said output comprising the output of said phase and frequency adjust network.

Claim 4

A method of effecting phase and frequency adjustments in a multiple frequecy digital phase-locked loop which includes a phase comparator having data and loop inputs, and a phase and frequency adjust network having a composite output signal, said method comprising the steps of: (a) generating a reference clocck signal; (b) generating a programmably divided clock signal from said reference clock signal in accordance with a divider ratio controlled by a first programmable signal; (c) generating a derived clock signal and a shifted derived clock signal from said programmably divided clock signal, said derived clock signal and said shifted derived clock signal operating at the same frequency and exhibiting a relatively narrow duty cycle, wherein said shifted derived clock signal is in delayed-time relation with respect to said derived clock signal; (d) inputting to said phase and frequency adjust network a second programmable signal, indicative of positive or negative frequency shifts and further inputting a third programmable signal comprising the output signal generated by said phase comparator indicitive of positive or negative phase shifts, said third programmable signal based on a phase comparison between said data and loop inputs; (e) generating a composite clock signal by selectively combining or subtracting said derived clock signal and said shifted derived clock signal periodically, at a rate defined by said programmably divided clock signal to effect frequency adjustments and selectively combining or subtracting said derived clock signal and said shifted derived clock signal on an individual pulse basis, independently of said frequency adjustments, to effect phase adjustments, said composite clock signal comrising the composite output signal of said phase and frequency adjust network.

Claim 5

A method of effecting phase and frequency adjustments in a multiple frequecy digital phase-locked loop which includes a phase comparator having data and loop inputs, and a phase and frequency adjust network having a composite output signal, said method comprising the steps of: (a) generating a reference clocck signal; (b) generating a programmably divided clock signal from said reference clock signal in accordance with a divider ratio controlled by a first programmable signal; (c) generating a derived clock signal and a shifted derived clock signal from said programmably divided clock signal, said derived clock signal and said shifted derived clock signal operating at the same frequency and exhibiting a relatively narrow duty cycle, wherein said shifted derived clock signal is in delayed-time relation with respect to said derived clock signal; (d) inputting to said phase and frequency adjust network a second programmable signal, indicative of positive or negative frequency shifts and further inputting a third programmable signal comprising the output signal generated by said phase comparator indicitive of positive or negative phase shifts, said third programmable signal based on a phase comparison between said data and loop inputs; (e) generating a composite clock signal by selectively combining or subtracting said derived clock signal and said shifted derived clock signal periodically, at a rate defined by said programmably divided clock signal to effect frequency adjustments and selectively combining or subtracting said derived clock signal and said shifted derived clock signal on an individual pulse basis, independently of said frequency adjustments, to effect phase adjustments, said composite clock signal comrising the composite output signal of said phase and frequency adjust network.