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US6165836A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Assignee: Micron Technology Inc
•
Filing: 1998-08-24
•
Granted: 2000-12-26
•
Expires: 2018-08-24
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Abstract

Abstract A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

Inventors

  • 👤 Leonard Forbes
  • 👤 Wendell P. Noble

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 10:41
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 168 words
A method of fabricating a memory array, the method comprising the steps of: forming a number of access transistors, each access transistor formed in a pillar of semiconductor material that extends outwardly from a substrate wherein the access transistor includes a first source/drain region, a body region and a second source/drain region formed vertically thereupon; forming a trench capacitor for each access transistor, wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor; forming a number of word lines that interconnect the gates of a number of access transistors to form a row of the array, the word lines disposed in a number of trenches that separate adjacent rows of access transistors; forming a number of body address lines that interconnect body regions of access transistors along the rows of the array; and forming a number of bit lines that interconnect second source/drain regions of selected access transistors so as to form a number of columns of the array.
Claim 2
Independent Claim 168 words
A method of fabricating a memory array, the method comprising the steps of: forming a number of access transistors, each access transistor formed in a pillar of semiconductor material that extends outwardly from a substrate wherein the access transistor includes a first source/drain region, a body region and a second source/drain region formed vertically thereupon; forming a trench capacitor for each access transistor, wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor; forming a number of word lines that interconnect the gates of a number of access transistors to form a row of the array, the word lines disposed in a number of trenches that separate adjacent rows of access transistors; forming a number of body address lines that interconnect body regions of access transistors along the rows of the array; and forming a number of bit lines that interconnect second source/drain regions of selected access transistors so as to form a number of columns of the array.
Claim 3
Dependent Claim 27 words
The method of claim 1, wherein the step of forming a trench capacitor further includes the step of forming a second plate that surrounds the first plate.
Claim 4
Dependent Claim 28 words
The method of claim 1, and further comprising the step of forming a contact that couples a second plate of the trench capacitor to an underlying semiconductor layer.
Claim 5
Dependent Claim 46 words
The method of claim 1, where the step of forming a trench capacitor comprises the step of forming a second plate that forms a grid pattern in a layer of semiconductor material such that the grid surrounds each of the pillars that form the access transistors.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-12-26 2004-06-26 2004-12-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-12-26 2008-06-26 2008-12-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-12-26 2012-06-26 2012-12-26 $7700.00 Window Closed / Lapsed

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