Patent US1140424A successfully refreshed from Google Patents.
US6014759A
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US
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Method and apparatus for transferring test data from a memory array
Assignee: Round Rock Research LLC
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Filing: 1997-06-13
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Granted: 2000-01-11
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Expires: 2017-06-13
Abstract
Abstract A memory device includes an output data path that uses single-ended data in conjunction with a flag signal. The output data path transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern if the data does not match the desired pattern outputs the flag signal. The flag signal is input to the output buffer and the output buffer outputs a tri-state condition on the data bus. Since the flag signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:01
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
177 words
A memory device, comprising: an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal and to produce output data corresponding to input data in the absence of the error signal; a memory array having a plurality of memory cells arranged in rows and columns; an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells in the memory array; a data path coupled between the I/O interface and the data input terminal of the output driver circuit; a comparing circuit coupled to the I/O interface, the comparing circuit comparing the data read from the plurality of memory cells to error criteria and producing the error signal in response to the data meeting the error criteria; and an error line coupled between the comparing circuit and the error input terminal.
Claim 2
Dependent Claim
177 words
A memory device, comprising: an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal and to produce output data corresponding to input data in the absence of the error signal; a memory array having a plurality of memory cells arranged in rows and columns; an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells in the memory array; a data path coupled between the I/O interface and the data input terminal of the output driver circuit; a comparing circuit coupled to the I/O interface, the comparing circuit comparing the data read from the plurality of memory cells to error criteria and producing the error signal in response to the data meeting the error criteria; and an error line coupled between the comparing circuit and the error input terminal.
Claim 3
Dependent Claim
17 words
The memory device of claim 1 wherein the I/O interface is substantially adjacent to the memory array.
Claim 4
Dependent Claim
17 words
The memory device of claim 2 wherein the comparing circuit is substantially adjacent to the memory array.
Claim 5
Dependent Claim
21 words
The memory device of claim 1, further including an error register coupled between the error line and the error input terminal.
Claim 6
Dependent Claim
19 words
The memory device of claim 1, further comprising a multiplexer coupled between the I/O interface and the data paths.
Claim 7
Dependent Claim
25 words
The memory device of claim 1, further comprising a plurality of data registers coupled between each of the data paths and the output driver circuit.
Claim 8
Dependent Claim
13 words
The memory device of claim 6 wherein the data registers are serially coupled.
Claim 9
Dependent Claim
25 words
The memory device of claim 6, further comprising a multiplexer coupled between a first plurality of the data paths and a first of the registers.
Claim 10
Dependent Claim
31 words
The memory device of claim 1 wherein the comparing circuit is configured to compare a plurality of read data to a select pattern of read data to identify the error condition.
Claim 11
Dependent Claim
210 words
A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; a storage device coupled to the processor; a data bus coupled to the processor; and a memory device, including: an output driver circuit having a data output terminal coupled to the data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal and to produce output data corresponding to input data in the absence of the error signal; a memory array having a plurality of memory cells arranged in rows and columns; an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells in the memory array; a data path coupled between the I/O interface and the data input terminal of the output driver circuit; a comparing circuit coupled to the I/O interface, the comparing circuit comparing the data read from the plurality of memory cells to error criteria and producing the error signal in response to the data meeting the error criteria; and an error line coupled between the comparing circuit and the error input terminal.
Claim 12
Dependent Claim
210 words
A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; a storage device coupled to the processor; a data bus coupled to the processor; and a memory device, including: an output driver circuit having a data output terminal coupled to the data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal and to produce output data corresponding to input data in the absence of the error signal; a memory array having a plurality of memory cells arranged in rows and columns; an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells in the memory array; a data path coupled between the I/O interface and the data input terminal of the output driver circuit; a comparing circuit coupled to the I/O interface, the comparing circuit comparing the data read from the plurality of memory cells to error criteria and producing the error signal in response to the data meeting the error criteria; and an error line coupled between the comparing circuit and the error input terminal.
Claim 13
Dependent Claim
17 words
The computer system of claim 10 wherein the I/O interface is substantially adjacent to the memory array.
Claim 14
Dependent Claim
17 words
The computer system of claim 10 wherein the comparing circuit is substantially adjacent to the memory array.
Claim 15
Dependent Claim
180 words
A test system including: a memory device including: an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal; a memory array arranged in rows and columns; an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of rows or columns, the I/O interface including a plurality of output terminals; a plurality of data paths coupled between the I/O interface and the output driver circuit; a comparing circuit coupled to the I/O interface, the comparing circuit being responsive an error condition at the I/O interface to produce the error signal; an error line coupled between the comparing circuit and the error input terminal; a test head adapted for coupling to the output driver circuit, the test head for detecting the tri-state condition of the output driver circuit; and testing circuitry coupled to the test head.
Claim 16
Dependent Claim
180 words
A test system including: a memory device including: an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal; a memory array arranged in rows and columns; an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of rows or columns, the I/O interface including a plurality of output terminals; a plurality of data paths coupled between the I/O interface and the output driver circuit; a comparing circuit coupled to the I/O interface, the comparing circuit being responsive an error condition at the I/O interface to produce the error signal; an error line coupled between the comparing circuit and the error input terminal; a test head adapted for coupling to the output driver circuit, the test head for detecting the tri-state condition of the output driver circuit; and testing circuitry coupled to the test head.
Claim 17
Dependent Claim
22 words
The system of claim 13 wherein the memory device further comprises a multiplexer coupled between the I/O interface and the data paths.
Claim 18
Dependent Claim
29 words
The test system of claim 13 wherein the memory device further comprises a plurality of data registers coupled between each of the data paths and the output driver circuit.
Claim 19
Dependent Claim
13 words
The test system of claim 15 wherein the data registers are serially coupled.
Claim 20
Dependent Claim
31 words
The test system of claim 13 wherein the comparing circuit is configured to compare a plurality of read data to a select pattern of read data to identify the error condition.
Claim 21
Dependent Claim
207 words
A data transfer circuit coupled between a memory array containing a plurality of memory cells arranged in rows and columns, and a least one data output terminal, the data transfer circuit comprising: a read circuit adapted for coupling to the memory array and having a data output terminal and an error signal output, the read circuit being responsive to a test read command to output data at the data output terminal from a plurality of the memory cells, and to output an error signal at the error output during the time that the read data is being output from the memory array if the read data is in error; an output driver circuit having an error input terminal, a data input terminal and an output terminal adapted for coupling to a respective data output terminal, the driver circuit to produce an output signal corresponding to the output data responsive to the absence of the error signal and to produce an output signal corresponding to an error condition responsive to the error signal; a data line extending between the read circuit data output terminal and the data input terminal of the output driver circuit; and an error line extending between the error output and the error input terminal.
Claim 22
Dependent Claim
207 words
A data transfer circuit coupled between a memory array containing a plurality of memory cells arranged in rows and columns, and a least one data output terminal, the data transfer circuit comprising: a read circuit adapted for coupling to the memory array and having a data output terminal and an error signal output, the read circuit being responsive to a test read command to output data at the data output terminal from a plurality of the memory cells, and to output an error signal at the error output during the time that the read data is being output from the memory array if the read data is in error; an output driver circuit having an error input terminal, a data input terminal and an output terminal adapted for coupling to a respective data output terminal, the driver circuit to produce an output signal corresponding to the output data responsive to the absence of the error signal and to produce an output signal corresponding to an error condition responsive to the error signal; a data line extending between the read circuit data output terminal and the data input terminal of the output driver circuit; and an error line extending between the error output and the error input terminal.
Claim 23
Dependent Claim
35 words
The data transfer circuit of claim 18 wherein the reading circuit includes a comparing circuit configured to compare the output data signals to a desired pattern and to produce the error signal in response thereto.
Claim 24
Dependent Claim
15 words
The data transfer circuit of claim 18 wherein the data lines are single-ended data lines.
Claim 25
Dependent Claim
16 words
The data transfer circuit of claim 20 wherein the error line is a single-ended data line.
Claim 26
Dependent Claim
25 words
The data transfer circuit of claim 18, further including a plurality of output data registers coupled between the data lines and the output driver circuit.
Claim 27
Dependent Claim
22 words
The data transfer circuit of claim 22, further including an error register coupled between the error line and the error input terminal.
Claim 28
Dependent Claim
21 words
The data transfer circuit of claim 23 wherein the number of data registers is greater than the number of error registers.
Claim 29
Dependent Claim
16 words
The data transfer circuit of claim 18 wherein the output driver circuit includes a tri-state buffer.
Claim 30
Dependent Claim
22 words
The data transfer circuit of claim 25 wherein the tri-state buffer is responsive to the error signal to produce a tri-state output.
References Cited (Backward Citations)
US35934A
Cited
US4096402A
Cited
US4404474A
Cited
US4611337A
Cited
US4638187A
Cited
US4638187B1
Cited
US4789796A
Cited
US4928281A
Cited
US5636163A
Cited
US4884270A
Cited
US5111435A
Cited
US4984204A
Cited
JPH02112317A
Cited
US4958088A
Cited
US5165046A
Cited
US5179298A
Cited
US5239206A
Cited
EP0450871A2
Cited
US5513327A
Cited
US5473575A
Cited
US5134311A
Cited
US5471591A
Cited
JPH04135311A
Cited
US5122690A
Cited
US5281865A
Cited
US5128563A
Cited
US5387809A
Cited
US5150186A
Cited
US5128560A
Cited
US5220208A
Cited
US5194765A
Cited
US5276642A
Cited
JPH05136664A
Cited
US5440260A
Cited
US5498990A
Cited
US5321368A
Cited
US5361002A
Cited
US5278460A
Cited
US5390308A
Cited
US5254883A
Cited
US5475642A
Cited
US5274276A
Cited
US5631871A
Cited
US5311481A
Cited
US5467473A
Cited
US5347177A
Cited
USRE35934E
Cited
US5347179A
Cited
US5506814A
Cited
US5383157A
Cited
US5483497A
Cited
EP0655741A2
Cited
US5590073A
Cited
US5574698A
Cited
US5400283A
Cited
US5438545A
Cited
US5508638A
Cited
EP0680049A2
Cited
US5457407A
Cited
EP0692872A2
Cited
US5694065A
Cited
US5619473A
Cited
US5627780A
Cited
US5568077A
Cited
US5497127A
Cited
US5847577A
Cited
US5621690A
Cited
US5638335A
Cited
US5581197A
Cited
US5576645A
Cited
US5636173A
Cited
US5655105A
Cited
US5578941A
Cited
US5737276A
Cited
US5636174A
Cited
US5627791A
Cited
US5668763A
Cited
US5854911A
Cited
US5831929A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |