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EP0692872A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Scannable master slave latch actuated by single phase clock

Assignee: International Business Machines Corp
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Filing: 1995-06-16
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Granted: —
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Expires: 2015-06-16
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Abstract

Abstract A device which includes a plurality of master/slave stages, each master/slave stage includes a master segment and at least one slave segment. Each master segment (excluding the one including a first master/slave stage) may be actuated by either external logic during normal operation, or by the output of a preceding slave segment during a scan operation. A continuous single phase clock provides clocked signals to a scan port, as well as the master segment and the slave segment in each of said master/slave stages. A control portion deactivates logic applied to the master segments, and actuates logic applied from the scan port to said master segments during all scan enable periods. The control portion also deactivates the scan port from the master segment, and activates the logic output to the master segments during all normal operation periods.

Inventors

  • 👤 Chih-Liang Chen

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-04 06:52
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3562; H03K3/35625; H03K3/356017; H03K3/356034; H03K3/356043

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 65 words
A master/slave latch circuit comprising: a master latch including a first cross-coupled inverter portion and a n-channel complementary write circuit; a slave latch whose input is an output from said master latch, the slave latch includes a second cross-coupled inverter portion and a p-channel complementary write circuit; and a single phase clock, which actuates said n-channel complementary write circuit and said p-channel complementary write circuit.
Claim 2
Dependent Claim 42 words
The master/slave latch circuit as described in claim 1, wherein said n-channel complementary write circuit comprises: a pair of n-channel transistors having their sources selectively connected to Vdd via an n-channel switch, the n-channel switch being controlled by said single phase clock.
Claim 3
Dependent Claim 41 words
The apparatus as described in claim 1, wherein said p-channel complementary write circuit comprises: a pair of p-channel transistors having their sources selectively connected to V DD via an p-channel switch, the p-channel switch being controlled by said single phase clock.
Claim 4
Dependent Claim 155 words
A circuit arrangement comprising: one or more of master/slave stages, each master/slave stage including a master segment and at least one slave segment, each master segment, excluding a master segment associated with the first master/slave stage, may be actuated by a signal from external logic in a first mode of operation, or by an output of a preceding slave segment during a second mode of operation; a continuous single phase clock signal which provides clocked signals to a scan port, as well as to the master segment and the slave segment in each of said master/slave stages; and control means, utilizing said scan port, for deactivating signals applied to said master segments, and actuating signals applied from the scan port to said master segments when in said second mode; said control means further deactivating said scan port from said master segment, and activating said logic output to said master segment, when in said first mode.
Claim 5
Dependent Claim 37 words
The circuit arrangement as described in claim 4, further comprising: clock limiting means for limiting the application of the clock signal to the scan port during periods when said master segment is the second mode of operation.

References Cited (Backward Citations)

US5036217A Cited

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