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EP0680049A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Synchronizer

Assignee: Mosaid Technologies Inc
•
Filing: 1994-12-09
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Granted: —
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Expires: 2014-12-09
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Abstract

Abstract A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) comprised of a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch.

Inventors

  • 👤 Bruce Millar
  • 👤 Richard C. Foss
  • 👤 Tomasz Wojcicki

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 16:04
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 171 words
A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) comprising: a) a complementary pair of data inputs for receiving data pulses, b) a clock input for receiving clock pulses, c) a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, d) means for applying data pulses from the complementary data inputs to the inputs of the capture latch, e) means for triggering the capture latch from the clock pulses, and f) means for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following said leading edge of a clock pulse and said one polarity of the data pulse the complementary outputs remain driven by the holding latch.
Claim 2
Dependent Claim 30 words
A circuit as defined in claim 1 in which drive current of said outputs is lower when driven by the holding latch than when driven by flip flop output drivers.
Claim 3
Dependent Claim 20 words
A circuit as defined in claim 2 in which the holding latch is comprised of a pair of crosscoupled inverters.
Claim 4
Dependent Claim 44 words
A circuit as defined in claim 1 in which one of said complementary data inputs is connected to a voltage reference, and further including means for providing one polarity of data pulses to another of said complementary data inputs of the flip flop circuit.
Claim 5
Dependent Claim 57 words
A circuit as defined in claim 4, in which the voltage reference is comprised of a complementary pair of field effect transistors having their gates and drains connected together and to said complementary data input, one of said transistors having its source connected to a source of voltage and the other having its source connected to ground.
Claim 6
Dependent Claim 25 words
A circuit as defined in claim 1 in which one of the data pulses is virtually infinitely long, being formed as a constant reference voltage.

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