US4928281A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1987-06-10
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Granted: 1990-05-22
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Expires: 2007-06-10
Abstract
Abstract A semiconductor memory includes a memory array which outputs storage data, at least one data unit at a time, each data unit having a plurality of bits including a parity bit, a parity check circuit for performing a parity check on storage data, at least one data unit at a time, input for both to and output from the memory array, and an external terminal for outputting the result of the parity check.
Inventors
- 👤 Hinoko Kurosawa
- 👤 Kazuya Itoh
- 👤 Hisashi Nakamura
- 👤 Masamichi Ishihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
254 words
A semiconductor memory comprising: a memory array which outputs storage data, at least one data unit at a time, each data unit having a plurality of bits including a parity bit; a first parity check circuit for performing parity check on storage data, at least one data unit at a time, output from said memory array; an external terminal means for outputting the result of said parity check; and a second parity check circuit for performing parity check on input data, at least one data unit at a time, written into said memory array, each of said input data units having a plurality of bits including a parity bit, wherein said first parity check circuit is also used as said second parity check circuit; means for inhibiting an operation of writing said input data with respect to said memory array when a parity error is generated; wherein said semiconductor memory is a static type RAM formed on one chip, and wherein said parity bit is added from a device which is provided outside said semiconductor memory; and wherein said external terminal means for outputting the result of said parity check includes means for inputting/outputting said parity bit, and the level of said external terminal means is changed to either a low or high level in accordance with the level of said parity bit when the result of said parity check is found to be normal, whereas, when a parity error is detected, the level of said external terminal is brought into a high-impedance state.
Claim 2
Dependent Claim
254 words
A semiconductor memory comprising: a memory array which outputs storage data, at least one data unit at a time, each data unit having a plurality of bits including a parity bit; a first parity check circuit for performing parity check on storage data, at least one data unit at a time, output from said memory array; an external terminal means for outputting the result of said parity check; and a second parity check circuit for performing parity check on input data, at least one data unit at a time, written into said memory array, each of said input data units having a plurality of bits including a parity bit, wherein said first parity check circuit is also used as said second parity check circuit; means for inhibiting an operation of writing said input data with respect to said memory array when a parity error is generated; wherein said semiconductor memory is a static type RAM formed on one chip, and wherein said parity bit is added from a device which is provided outside said semiconductor memory; and wherein said external terminal means for outputting the result of said parity check includes means for inputting/outputting said parity bit, and the level of said external terminal means is changed to either a low or high level in accordance with the level of said parity bit when the result of said parity check is found to be normal, whereas, when a parity error is detected, the level of said external terminal is brought into a high-impedance state.
Claim 3
Dependent Claim
167 words
A semiconductor memory formed on one chip comprising: parity check means for performing parity check based on data comprised of a plurality of bits and parity information comprised of at least one bit; memory means coupled to said parity check means; first external terminal means coupled to said parity check means and said memory means; and writing means for controlling a writing operation of said memory means based on an output signal of said parity check means, wherein said parity check means performs a parity check based on said data and said parity information supplied from said external terminal means within a period of a write operation mode of said semiconductor memory and a parity check based on said data and said parity information read from said memory means within a period of a read operation mode of said semiconductor memory, and wherein said writing means inhibits said writing operation of said memory means when said output signal of said parity check means indicates a parity error.
Claim 4
Dependent Claim
167 words
A semiconductor memory formed on one chip comprising: parity check means for performing parity check based on data comprised of a plurality of bits and parity information comprised of at least one bit; memory means coupled to said parity check means; first external terminal means coupled to said parity check means and said memory means; and writing means for controlling a writing operation of said memory means based on an output signal of said parity check means, wherein said parity check means performs a parity check based on said data and said parity information supplied from said external terminal means within a period of a write operation mode of said semiconductor memory and a parity check based on said data and said parity information read from said memory means within a period of a read operation mode of said semiconductor memory, and wherein said writing means inhibits said writing operation of said memory means when said output signal of said parity check means indicates a parity error.
Claim 5
Dependent Claim
34 words
A semiconductor memory according to claim 2, further comprising second external terminal means coupled to said parity check means for delivering said output signal of said parity check means outside of said semiconductor memory.
Claim 6
Dependent Claim
30 words
A semiconductor memory according to claim 3, further comprising output means for transmitting said data and said parity information read from said memory means to said first external terminal means.
Claim 7
Dependent Claim
34 words
A semiconductor memory according to claim 4, wherein said writing means include input means for controlling transmission of said data and said parity information supplied from said first external terminal means to said memory.
Claim 8
Dependent Claim
34 words
A semiconductor memory according to claim 5, wherein said input means inhibits said transmission of said data and said parity information when said output signal of said parity check means indicates a parity error.
Claim 9
Dependent Claim
15 words
A semiconductor memory according to claim 6, said memory means is a static type RAM.
Claim 10
Dependent Claim
191 words
A microcomputer system comprising: a microprocessor; a semiconductor memory formed on one chip; and bus means coupled to said microprocessor and said semiconductor memory, wherein said semiconductor memory comprises: parity check means for performing parity check based on data comprised of a plurality of bits and parity information comprised of at least one bit; memory means coupled to said parity check means; first external terminal means coupled to said bus means, said parity check means and said memory means; and writing means for controlling a writing operation of said memory means based on an output signal of said parity check means, wherein said parity check means performs a parity check based on said data and said parity information supplied from said external terminal means within a period of a write operation mode of said semiconductor memory and a parity check based on said data and said parity information read from said memory means within a period of a read operation mode of said semiconductor memory, and wherein said writing means inhibits said writing operation of said memory means when said output signal of said parity check means indicates a parity error.
Claim 11
Dependent Claim
191 words
A microcomputer system comprising: a microprocessor; a semiconductor memory formed on one chip; and bus means coupled to said microprocessor and said semiconductor memory, wherein said semiconductor memory comprises: parity check means for performing parity check based on data comprised of a plurality of bits and parity information comprised of at least one bit; memory means coupled to said parity check means; first external terminal means coupled to said bus means, said parity check means and said memory means; and writing means for controlling a writing operation of said memory means based on an output signal of said parity check means, wherein said parity check means performs a parity check based on said data and said parity information supplied from said external terminal means within a period of a write operation mode of said semiconductor memory and a parity check based on said data and said parity information read from said memory means within a period of a read operation mode of said semiconductor memory, and wherein said writing means inhibits said writing operation of said memory means when said output signal of said parity check means indicates a parity error.
Claim 12
Dependent Claim
37 words
A semiconductor memory according to claim 8, further comprising a second external terminal means coupled to said bus means and said parity check means for delivering said output signal of said parity check means to said microprocessor.
Claim 13
Dependent Claim
30 words
A semiconductor memory according to claim 9, further comprising output means for transmitting said data and said parity information read from said memory means to said first external terminal means.
Claim 14
Dependent Claim
34 words
A semiconductor memory according to claim 10, wherein said writing means includes input means for controlling transmission of said data and said parity information supplied from said first external terminal means to said memory.
Claim 15
Dependent Claim
29 words
A semiconductor memory according to claim 11, wherein said input means inhibits said transmission of said data and said parity information when said output signal indicates a parity error.
Claim 16
Dependent Claim
15 words
A semiconductor memory according to claim 12, said memory means is a static type RAM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-21 | 1993-11-20 | 1994-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-21 | 1997-11-20 | 1998-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-21 | 2001-11-20 | 2002-05-22 | $7700.00 | Window Closed / Lapsed |