US3789204A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-checking digital storage system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1972-06-06
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Granted: 1974-01-29
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Expires: 1992-06-06
Abstract
Abstract A self-checking digital storage system and method for detecting faults within the storage system. An address word for a memory location into which information is to be written is combined with a data word that is contained in that address location and one combined parity bit is generated for the combined words and placed into memory. When the information is accessed, the address information is subtracted from the data information to indicate correct data information if the data parity corresponds to the original data parity.
Inventors
- 👤 G Barlow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016; G06F11/1032
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
263 words
A self-checking digital storage system comprising: a. a memory array; b. half-adder and half-subtractor circuit means coupled to said memory array; c. data parity generating means, coupled to said half-adder circuit means, for generating a data parity bit indicative of the parity of data to be stored in a selected location of said digital storage system; d. address parity generating means, coupled to said half-adder and half-subtractor circuit means, for generating a first address parity bit indicative of the parIty of an address where the data is to be stored or retrieved; e. parity checking means, coupled to said memory array and to said half-subtractor means, for comparing the data parity applied or retrieved to or from said address location of said memory, with the data parity subtracted from an actually accessed location of said memory; f. data input means, coupled to said memory array and to said data parity generating means, for applying data signals to said memory array; and g. data output means, coupled to said memory array and to said parity checking means, for abstracting data signals from said memory array; whereby said half-adder circuit means half-adds the data parity bit and the first address parity bit to produce a combined parity bit for storing in the addressed location within said memory array and whereby said half-subtractor circuit means half-subtracts from a memory-accessed combined parity bit a second generated address parity bit indicative of the parity of the address of the addressed location, said combined parity bit indicative of the parity of the data and address in the accessed location.
Claim 2
Dependent Claim
263 words
A self-checking digital storage system comprising: a. a memory array; b. half-adder and half-subtractor circuit means coupled to said memory array; c. data parity generating means, coupled to said half-adder circuit means, for generating a data parity bit indicative of the parity of data to be stored in a selected location of said digital storage system; d. address parity generating means, coupled to said half-adder and half-subtractor circuit means, for generating a first address parity bit indicative of the parIty of an address where the data is to be stored or retrieved; e. parity checking means, coupled to said memory array and to said half-subtractor means, for comparing the data parity applied or retrieved to or from said address location of said memory, with the data parity subtracted from an actually accessed location of said memory; f. data input means, coupled to said memory array and to said data parity generating means, for applying data signals to said memory array; and g. data output means, coupled to said memory array and to said parity checking means, for abstracting data signals from said memory array; whereby said half-adder circuit means half-adds the data parity bit and the first address parity bit to produce a combined parity bit for storing in the addressed location within said memory array and whereby said half-subtractor circuit means half-subtracts from a memory-accessed combined parity bit a second generated address parity bit indicative of the parity of the address of the addressed location, said combined parity bit indicative of the parity of the data and address in the accessed location.
Claim 3
Dependent Claim
19 words
A self-checking digital storage system as recited in claim 1 wherein said parity checking means comprises a parity generator.
Claim 4
Dependent Claim
20 words
A self-checking digital storage system as recited in claim 1 wherein said half-adder and half-subtractor circuit means comprise exclusive-OR circuitry.
Claim 5
Dependent Claim
20 words
A self-checking digital storage system as recited in claim 1 wherein said memory array is a solid state memory array.
Claim 6
Dependent Claim
28 words
A self-checking digital storage system as recited in claim 1 including decoding means coupled to said memory array for decoding the selected address location of said memory array.
Claim 7
Dependent Claim
19 words
A self-checking digital storage system as recited in claim 1 wherein said memory array is a core memory array.
Claim 8
Dependent Claim
20 words
A self-checking digital storage system as recited in claim 1 wherein said memory array is a read only memory (ROM).
Claim 9
Dependent Claim
20 words
A self-checking digital storage system as recited in claim 1 wherein said memory array is a random access memory (RAM).
Claim 10
Dependent Claim
20 words
A self-checking digital storage system as recited in claim 1 wherein said memory array is a content addressable memory (CAM).
Claim 11
Independent Claim
162 words
A method of checking a digital storage system comprising the steps of: a. generating a data parity bit indicative of the parity of the data to be stored in said digital storage system; b. generating a first address parity bit indicative of the parity of the address where the data is to be stored; c. half-adding the data parity bit and the address parity bit to produce a combined parity bit; d. storing the combined parity bit and the data in a selected location addressed by the address; e. accessing the combined parity bit along with the data whenever the data is readout of said digital storage system; f. generating a second address parity bit for the address uitlized to effect the readout of the data and the combined parity bit; g. half-subtracting the second address parity bit from the combined parity to produce a reconstructed parity bit; and, h. comparing the reconstructed parity with a parity bit of the data output.
Claim 12
Independent Claim
162 words
A method of checking a digital storage system comprising the steps of: a. generating a data parity bit indicative of the parity of the data to be stored in said digital storage system; b. generating a first address parity bit indicative of the parity of the address where the data is to be stored; c. half-adding the data parity bit and the address parity bit to produce a combined parity bit; d. storing the combined parity bit and the data in a selected location addressed by the address; e. accessing the combined parity bit along with the data whenever the data is readout of said digital storage system; f. generating a second address parity bit for the address uitlized to effect the readout of the data and the combined parity bit; g. half-subtracting the second address parity bit from the combined parity to produce a reconstructed parity bit; and, h. comparing the reconstructed parity with a parity bit of the data output.
Claim 13
Dependent Claim
29 words
The method as recited in claim 10 including the further step of comparing the reconstructed parity bit to the parity bit of the word stored in the memory array.
Claim 14
Independent Claim
116 words
A method of checking a digital storage system comprising the steps of: a. combining two words to obtain a combined bit indicative of the parity of each of the two words; b. storing said combined bit in a location of the digital storage system together with one of the two words; c. accessing said combined bit together with said one of two words when the location containing said combined bit and one word is addressed by the other word; d. reconstructing the parity bit of the one word from the combined bit and the parity bit of the other word; e. and comparing the reconstructed parity bit to the original parity bit of The one word.
Claim 15
Independent Claim
116 words
A method of checking a digital storage system comprising the steps of: a. combining two words to obtain a combined bit indicative of the parity of each of the two words; b. storing said combined bit in a location of the digital storage system together with one of the two words; c. accessing said combined bit together with said one of two words when the location containing said combined bit and one word is addressed by the other word; d. reconstructing the parity bit of the one word from the combined bit and the parity bit of the other word; e. and comparing the reconstructed parity bit to the original parity bit of The one word.
Claim 16
Dependent Claim
96 words
A self-checking digital storage system comprising, combining means, coupled to said digital storage system, for combining the parity bit of one word with the parity bit of another word to obtain a combined bit, reconstructing means, coupled to said combining means and to said digital storage system, for reconstructing the parity bit of the one word from the combined bit and a generated bit of said another word, and comparing means, coupled to said reconstructing means and to said digital storage system, for comparing the reconstructed parity bit to the parity bit of the one word.
Claim 17
Dependent Claim
96 words
A self-checking digital storage system comprising, combining means, coupled to said digital storage system, for combining the parity bit of one word with the parity bit of another word to obtain a combined bit, reconstructing means, coupled to said combining means and to said digital storage system, for reconstructing the parity bit of the one word from the combined bit and a generated bit of said another word, and comparing means, coupled to said reconstructing means and to said digital storage system, for comparing the reconstructed parity bit to the parity bit of the one word.
Claim 18
Dependent Claim
21 words
A self-checking digital storage system as recited in claim 13 wherein said combined bit is stored in said digital storage system.
Claim 19
Dependent Claim
43 words
A self-checking digital storage system as recited in claim 14 wherein the one word is a data word and the other word is an address word indicating a storage location in said digital storage system where said combined bit is to be stored.
Claim 20
Dependent Claim
221 words
A self-checking digital storage system comprising: a. a memory array; b. half-adder and half-subtractor circuit means, the output of said half-adder and at least one input of said half-subtractor coupled to said memory array for storing or retrieving information in or out of said memory array; c. data parity generating means coupled to said half-adder circuit means for generating a data parity bit indicative of the parity of data to be stored in a selected location of said memory array; d. address parity generating means, coupled to said half-adder and half-subtractor circuit means, for generating a first address parity bit indicative of the parity of an address where the data is to be stored or retrieved; whereby said half-adder circuit means half-adds the data parity bit and the first address parity bit for storing in the addressed location within said memory array, and whereby said half-subractor circuit means half-subtracts from a memory-accessed combined parity bit a second generated address parity bit indicative of the parity of the address of the addressed location to produce reconstructed parity bit, said combined parity bit indicative of the parity of the data and address in the accessed location; and, e. comparator means, coupled to said half-subtractor and to said memory array, for comparing the reconstructed parity bit with the parity bit of the data output.
Claim 21
Dependent Claim
221 words
A self-checking digital storage system comprising: a. a memory array; b. half-adder and half-subtractor circuit means, the output of said half-adder and at least one input of said half-subtractor coupled to said memory array for storing or retrieving information in or out of said memory array; c. data parity generating means coupled to said half-adder circuit means for generating a data parity bit indicative of the parity of data to be stored in a selected location of said memory array; d. address parity generating means, coupled to said half-adder and half-subtractor circuit means, for generating a first address parity bit indicative of the parity of an address where the data is to be stored or retrieved; whereby said half-adder circuit means half-adds the data parity bit and the first address parity bit for storing in the addressed location within said memory array, and whereby said half-subractor circuit means half-subtracts from a memory-accessed combined parity bit a second generated address parity bit indicative of the parity of the address of the addressed location to produce reconstructed parity bit, said combined parity bit indicative of the parity of the data and address in the accessed location; and, e. comparator means, coupled to said half-subtractor and to said memory array, for comparing the reconstructed parity bit with the parity bit of the data output.
References Cited (Backward Citations)
US3599146A
Cited
US3585378A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |