Error detection scheme for memories

Claim 3

A method as set forth in claim 1 wherein the address parity is determined by generating the parity of the actual address stored in the memory address register and determining the parity of the data word read out by generating the parity of the data word actually stored in the system data register.

Claim 4

A method as set forth in claim 2 wherein the parities of the address and data word are chosen to be equal and including the step of providing an extra check bit to be included with each data word in memory indicating the nature of the parity equality, and checking the contents of the check bit after each readout against the parities of said address and data word to ascertain whether an error that is present exists in the addressing circuitry or in the memory and data register circuitry.

Claim 5

A method as set forth in claim 3 including the additional step of providing a second check bit which is the complement of the first said check bit and the additional step of checking the two said check bits after each readout cycle to determine if they are equal and providing a system signal that a double word readout has occurred if both check bits are equal.

Claim 6

A memory system including an error detection mechanism; said memory system including an address register, decoding and addressing circuitry which cause a single fixed word to be read from the memory, a memory per se, sensing circuitry and a data register for said memory connected to the output of said sensing circuitry and in which memory data words are stored at predetermined addresses in said memory so that the parity of the data word bears a fixed predetermined relationship to the parity of the address of said word, means operable after a read cycle in the memory to determine the parity of the data currently stored in the data register, means concurrently operative with the previous means to determine the parity of the address currently in the address register, means to compare the two parties, and means operative to produce an ''''error'''' signal if the two parities do not have said fixed predetermined relationship to each other.

Claim 7

A memory system including an error detection mechanism; said memory system including an address register, decoding and addressing circuitry which cause a single fixed word to be read from the memory, a memory per se, sensing circuitry and a data register for said memory connected to the output of said sensing circuitry and in which memory data words are stored at predetermined addresses in said memory so that the parity of the data word bears a fixed predetermined relationship to the parity of the address of said word, means operable after a read cycle in the memory to determine the parity of the data currently stored in the data register, means concurrently operative with the previous means to determine the parity of the address currently in the address register, means to compare the two parties, and means operative to produce an ''''error'''' signal if the two parities do not have said fixed predetermined relationship to each other.

Claim 8

A memory system as set forth in claim 5 wherein the parties of the data words and addresses thereof are equal and wherein said last-named means includes means to produce an error signal whenever a parity inequality is detected.

Claim 9

A memory system as set forth in claim 6 wherein an additional check bit is included with each data word in memory, said check bit indicating whether the fixed predetermined relationship of parities is odd or even and means for comparing the two said parities with said check bit for correspondence.

Claim 10

A memory system as set forth in claim 7 wherein a second check bit is included in each data word and wherein the binary value stored in said second check bit is always the complement of the binary value stored in said first check bit and including means to compare the two check bits subsequent to a readout cycle and means to indicate a double word readout error whenever both of said check bits are a binary one.

Claim 11

A memory system as set forth in claim 6 wherein the two parity determining means are parity generators producing a predetermined binary value depending on whether or not odd or even parity is detected.

Claim 12

A memory system as set forth in claim 9 wherein said memory comprises a control memory for storing lists of computer instructions and wherein the data stored therein is essentially fixed.

Claim 13

A memory system as set forth in claim 10 wherein said memory is a read only store.