US4528666A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory system with built in parity
Assignee: Texas Instruments Inc
•
Filing: 1983-01-03
•
Granted: 1985-07-09
•
Expires: 2003-01-03
Abstract
Abstract A memory apparatus including an array of storage elements connected to several addressing lines for selectively connecting a group of the storage elements to multiple data lines. The memory apparatus further includes a parity circuit connected to the data lines and storage elements for selectively generating parity to designate the validity of the selected group of data connected in the portion of storage elements selected by the address lines and storing the parity in the array with the data. Control circuitry is further included for controlling the generation of parity by the parity circuit. The parity generation in this memory system is programmable according to control lines that are connected to the control circuit. The parity circuit may generate the parity output either in the same cycle as the memory access or in the next succeeding cycle of memory access. The output buffer for the parity signal may also be programmable in either a push-pull or a pull-down only configuration.
Inventors
- 👤 James H. Cline
- 👤 David M. Chastain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
132 words
A memory apparatus comprising: an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines; user programmable control circuit means for generating a first signal when a selected storage element within the selected group is selected to contain parity information, and for generating a second signal when the selected storage element within the selected group is selected to contain data information; parity circuit means connected to the data lines and the selected storage elements group for generating parity to designate validity of data within the selected group contained in the portion of storage elements selected by the address lines and storing the parity in the array with the data group when the first signal is generated.
Claim 2
Dependent Claim
132 words
A memory apparatus comprising: an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines; user programmable control circuit means for generating a first signal when a selected storage element within the selected group is selected to contain parity information, and for generating a second signal when the selected storage element within the selected group is selected to contain data information; parity circuit means connected to the data lines and the selected storage elements group for generating parity to designate validity of data within the selected group contained in the portion of storage elements selected by the address lines and storing the parity in the array with the data group when the first signal is generated.
Claim 3
Dependent Claim
52 words
A memory apparatus according to claim 1 wherein said control circuit means further includes means, operating only when the first signal is generated, for transmitting data stored in the selected group of storage elements along the data lines, and for storing the parity information for transmission after the transmission of the data.
Claim 4
Dependent Claim
44 words
A memory apparatus according to claim 2, further including an output buffer, and wherein said user programmable control circuit means further includes programmable circuit means for determining whether the output buffer for the parity circuit means is a push-pull buffer or a pull-down buffer.
Claim 5
Dependent Claim
25 words
A memory apparatus according to claim 3, wherein said parity circuit means further checks the parity of the data being accessed from said storage elements.
Claim 6
Dependent Claim
141 words
A memory apparatus comprising: an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines; parity circuit means connected to the data lines and selected storage elements for, in the presence of a first signal, selectively generating parity to designate validity of the selected group of data contained in the portion of storage elements selected by the address lines and storing the parity in the array with the data group; and control circuit means for generating the first signal responsive to a preselected user control signal, wherein said control circuit means includes programmable means for the selective generation of a parity bit in the presence of the first signal, and the selective storage of an additional data bit in the absence of the first signal.
Claim 7
Dependent Claim
141 words
A memory apparatus comprising: an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines; parity circuit means connected to the data lines and selected storage elements for, in the presence of a first signal, selectively generating parity to designate validity of the selected group of data contained in the portion of storage elements selected by the address lines and storing the parity in the array with the data group; and control circuit means for generating the first signal responsive to a preselected user control signal, wherein said control circuit means includes programmable means for the selective generation of a parity bit in the presence of the first signal, and the selective storage of an additional data bit in the absence of the first signal.
Claim 8
Dependent Claim
56 words
A memory apparatus according to claim 5, wherein said control circuit means provides for the transmission of data from the selected group of storage elements selected by the address lines, and for the transmission of the parity bit corresponding to the selected group after the transmission of the data in the presence of the first signal.
Claim 9
Dependent Claim
19 words
A memory apparatus according to claim 6, wherein said memory apparatus is monolithically integrated on a signal semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-08 | 1989-01-07 | 1989-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-08 | 1993-01-07 | 1993-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-08 | 1997-01-07 | 1997-07-09 | $7700.00 | Window Closed / Lapsed |