Method of and means for in-line testing of a memory operating in time-division mode

Claim 3

A method as defined in claim 1 wherein the reading phase of each time slot precedes the writing phase thereof whereby a data word inscribed in a memory stage during a given scanning cycle is retrieved therefrom during an immediately following scanning cycle, the replication of said inversion commands being delayed by one scanning cycle.

Claim 4

A method as defined in claim 2 wherein the addressing of said memory stages proceeds in a predetermined order in one part of each reading and writing phase of any scanning cycle and wherein other parts of said phases are available for out-of-turn reading and writing, comprising the further steps of comparing the address of a memory stage addressed out of turn with the address called for by said predetermined order and modifying the relative timing of a corresponding inversion command and its replication in accordance with the relative ranks of the compared addresses.

Claim 5

A method as defined in claim 3 wherein out-of-turn writing affects less than all the bits of a data word already inscribed in a given stage, comprising the further step of blocking said parity check on retrieving a data word altered by the out-of-turn writing.

Claim 6

A method as defined in claim 1 wherein said parity criteria are supplemental bits of a value determined by the combined bits of the data words to be inscribed and respective address codes identifying the corresponding memory stages, said parity check being carried out on combinations of retrieved data words and respective address codes.

Claim 7

In a data-handling system, in combination: a multistage memory provided with addressing means for periodically identifying the stages thereof in respective time slots of a recurrent cycle, input means for inscribing an incoming multibit data word in an identified memory stage during a writing phase of any time slot, and output means for retrieving an inscribed data word from an indentified memory stage during a reading phase of any time slot; first conductor means connected to said input means for delivering said incoming data words to said memory; second conductor means connected to said output means for reading out the data words retrieved from said memory; first selective inversion means inserted in said first conductor means; second selective inversion means inserted in said second conductor means; a supply of control signals synchronized with said scanning means connected to said first inversion means for selectively actuating same, during certain scanning cycles selected in a generally stochastic manner, to replace the bits of said incoming data words by their complements prior to inscription thereof in the respective memory stages, said supply being further connected to said second inversion means for selectively actuating same, in timed relationship with the actuation of said first inversion means, to reinvert inverted data words retrieved from said memory stages; bit-checking means connected to said first conductor means at a point between said first inversion means and said input means for supplementing said incoming data words with parity criteria written along with said data words in the respective memory stages; parity-check means connected to said second conductor means at a point between said output means and said second inversion means for verifying the correct operation of said memory; and alarm means connected to said parity-check means for indicating a malfunction upon a recurrent negative outcome of a parity check in any bit position in homologous time slots of consecutive scanning cycles.

Claim 8

In a data-handling system, in combination: a multistage memory provided with addressing means for periodically identifying the stages thereof in respective time slots of a recurrent cycle, input means for inscribing an incoming multibit data word in an identified memory stage during a writing phase of any time slot, and output means for retrieving an inscribed data word from an indentified memory stage during a reading phase of any time slot; first conductor means connected to said input means for delivering said incoming data words to said memory; second conductor means connected to said output means for reading out the data words retrieved from said memory; first selective inversion means inserted in said first conductor means; second selective inversion means inserted in said second conductor means; a supply of control signals synchronized with said scanning means connected to said first inversion means for selectively actuating same, during certain scanning cycles selected in a generally stochastic manner, to replace the bits of said incoming data words by their complements prior to inscription thereof in the respective memory stages, said supply being further connected to said second inversion means for selectively actuating same, in timed relationship with the actuation of said first inversion means, to reinvert inverted data words retrieved from said memory stages; bit-checking means connected to said first conductor means at a point between said first inversion means and said input means for supplementing said incoming data words with parity criteria written along with said data words in the respective memory stages; parity-check means connected to said second conductor means at a point between said output means and said second inversion means for verifying the correct operation of said memory; and alarm means connected to said parity-check means for indicating a malfunction upon a recurrent negative outcome of a parity check in any bit position in homologous time slots of consecutive scanning cycles.

Claim 9

The combination in claim 6 wherein said supply comprises a pseudo-randum generator of binary signals.

Claim 10

The combination as defined in claim 6 wherein said addressing means includes a binary counter emitting a succession of regular address codes in a predetermined order, a source of out-of-turn address codes, and switchover means operable to connect said counter to said memory in one part of each reading and writing phase and to connect said source to said memory in another part of at least some reading and writing phases; further comprising comparison means connected to receive said regular and out-of-turn address codes for determining their relative numerical values, and delay means controlled by said comparison means for modifying the relative timing of the actuation of said first and second inversion means in accordance with said relative numerical values.

Claim 11

The combination defined in claim 8 wherein said switchover means has a first input connection, energizable by said counter, a second input connection energizable by said source, and an output connection leading to said memory, said comparison means having input terminals tied to said first input connection and to said output connection.

Claim 12

The combination defined in claim 9 wherein said supply is provided with a first output lead carrying a first sequence of control signals and with a second output lead carrying a second sequence of control signals related to said first sequence but lagging same by one scanning cycle, said delay means including first switch means connected to said first output lead and second switch means connected to said second output lead, said first switch means being responsive to said comparison means for extending said second output lead to said first inversion means upon the regular address code preceding the out-of-turn address code in said predetermined order and for extending said first output lead to said first inversion means under all other conditions, said second switch means being responsive to said comparison means for extending said first output lead to said second inversion means upon the out-of-turn address code preceding the regular address code in said predetermined order and for extending said second output lead to said second inversion means under all other conditions.

Claim 13

The combination defined in claim 6, further comprising a first parity-bit inserter connected to said addressing means for receiving address codes of memory stages identified thereby, said bit-checking means including a second parity-bit inserter connected to said addressing means for receiving said address codes in addition to the incoming data words from said first conductor means, said parity-check means being connected to said addressing means for receiving said address codes in addition to the retrieved data words from said second conductor means.

Claim 14

The combination defined in claim 11 wherein said second parity-bit inserter and said parity-check means are connected to said addressing means by way of said first parity-bit inserter.