US3719929A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory analyzers
Assignee: Northrop Grumman Guidance and Electronics Co Inc
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Filing: 1971-08-11
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Granted: 1973-03-06
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Expires: 1991-08-11
Abstract
Abstract A memory analyzer is provided with a disturb mode for selectively writing complemented test data into a computer memory. The writing operation is repeated a number of times, for example, 5,000 write cycles, and the data is thereafter read out and compared to the original data to detect errors. Hence, the effect of repeated write operations in selected locations on data in non-selected locations can be determined. One feature resides in the provision of a ''''B increments A'''' mode whereby access to an A address register is incremented upon each cycle of access to a B address register.
Inventors
- 👤 R Fay
- 👤 G Simonetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
311 words
In a memory analyzer for analyzing the operability of a memory system for a computer, which memory system has a plurality of address and data lines, said analyzer having an address register connected to said address lines and having read/write control means for controlling the reading of information out of said memory system and for controlling the writing of information into said memory system, said analyzer including program means for establishing a predetermined program of addresses in said address register, and data generator means for establishing a predetermined program of data information on said data lines, the improvement comprising: disturb means including first control means capable of providing at least three distinguishable output conditions; selectable means operable to condition said first control means to provide a first outpuT condition; address selection means responsive to a second output condition of said first control means for selecting predetermined ones of the addresses in said address register; cycle means responsive to said second output condition of said first control means for cycling the selected addresses through a plurality of write cycles; second control means responsive to a third output condition of said first control means for conditioning said read/write control means to read information from said memory system; said first control means being responsive to the establishment of said predetermined program of addresses in said address register by said program means for changing the output condition of said first control means from its first to its second output condition, said first control means being further responsive to the completed write cycling of the selected addresses for changing the output condition of said first control means from its second to its third output condition; and error display means for comparing information stored in said memory system before said write cycling to information stored in said memory system after said write cycling to display descrepencies therebetween.
Claim 2
Dependent Claim
311 words
In a memory analyzer for analyzing the operability of a memory system for a computer, which memory system has a plurality of address and data lines, said analyzer having an address register connected to said address lines and having read/write control means for controlling the reading of information out of said memory system and for controlling the writing of information into said memory system, said analyzer including program means for establishing a predetermined program of addresses in said address register, and data generator means for establishing a predetermined program of data information on said data lines, the improvement comprising: disturb means including first control means capable of providing at least three distinguishable output conditions; selectable means operable to condition said first control means to provide a first outpuT condition; address selection means responsive to a second output condition of said first control means for selecting predetermined ones of the addresses in said address register; cycle means responsive to said second output condition of said first control means for cycling the selected addresses through a plurality of write cycles; second control means responsive to a third output condition of said first control means for conditioning said read/write control means to read information from said memory system; said first control means being responsive to the establishment of said predetermined program of addresses in said address register by said program means for changing the output condition of said first control means from its first to its second output condition, said first control means being further responsive to the completed write cycling of the selected addresses for changing the output condition of said first control means from its second to its third output condition; and error display means for comparing information stored in said memory system before said write cycling to information stored in said memory system after said write cycling to display descrepencies therebetween.
Claim 3
Dependent Claim
311 words
In a memory analyzer for analyzing the operability of a memory system for a computer, which memory system has a plurality of address and data lines, said analyzer having an address register connected to said address lines and having read/write control means for controlling the reading of information out of said memory system and for controlling the writing of information into said memory system, said analyzer including program means for establishing a predetermined program of addresses in said address register, and data generator means for establishing a predetermined program of data information on said data lines, the improvement comprising: disturb means including first control means capable of providing at least three distinguishable output conditions; selectable means operable to condition said first control means to provide a first outpuT condition; address selection means responsive to a second output condition of said first control means for selecting predetermined ones of the addresses in said address register; cycle means responsive to said second output condition of said first control means for cycling the selected addresses through a plurality of write cycles; second control means responsive to a third output condition of said first control means for conditioning said read/write control means to read information from said memory system; said first control means being responsive to the establishment of said predetermined program of addresses in said address register by said program means for changing the output condition of said first control means from its first to its second output condition, said first control means being further responsive to the completed write cycling of the selected addresses for changing the output condition of said first control means from its second to its third output condition; and error display means for comparing information stored in said memory system before said write cycling to information stored in said memory system after said write cycling to display descrepencies therebetween.
Claim 4
Dependent Claim
311 words
In a memory analyzer for analyzing the operability of a memory system for a computer, which memory system has a plurality of address and data lines, said analyzer having an address register connected to said address lines and having read/write control means for controlling the reading of information out of said memory system and for controlling the writing of information into said memory system, said analyzer including program means for establishing a predetermined program of addresses in said address register, and data generator means for establishing a predetermined program of data information on said data lines, the improvement comprising: disturb means including first control means capable of providing at least three distinguishable output conditions; selectable means operable to condition said first control means to provide a first outpuT condition; address selection means responsive to a second output condition of said first control means for selecting predetermined ones of the addresses in said address register; cycle means responsive to said second output condition of said first control means for cycling the selected addresses through a plurality of write cycles; second control means responsive to a third output condition of said first control means for conditioning said read/write control means to read information from said memory system; said first control means being responsive to the establishment of said predetermined program of addresses in said address register by said program means for changing the output condition of said first control means from its first to its second output condition, said first control means being further responsive to the completed write cycling of the selected addresses for changing the output condition of said first control means from its second to its third output condition; and error display means for comparing information stored in said memory system before said write cycling to information stored in said memory system after said write cycling to display descrepencies therebetween.
Claim 5
Dependent Claim
62 words
Apparatus according to claim 1 further including a data register connected to said data lines, said data generator means being adapted to establish said predetermined program of data information in said data register, and complement means responsive to said first output condition of said first control means for establishing the complement of said predetermined program of data information in said data register.
Claim 6
Dependent Claim
243 words
Apparatus according to claim 1 wherein said first control means comprises first and second bistable means each having a set input, a reset input, a first output and a second output, each of said first and second bistable means being responsive to a predetermined signal at its respective set input to discontinue a predetermined signal established at one of its outputs and to establish a predetermined signal at the other of its outputs, each of said first and second bistable means being further responsive to a predetermined signal at its respective reset input to discontinue any predetermined signal established at its second output and to establish a predetermined signal at its first output, the reset inputs of each of said first and second bistable means being connected to said selectable means, the second output of said first bistable means being connected to the set input of said second bistable means, first gate means connected to said address register for establishing a predetermined signal at the set input of said first bistable means, said first output condition of said first control means being established by predetermined signal at the first output of said second bistable means, said second output condition being established by predetermined signals at the first output of said first bistable means and the second output of said second bistable means, and the third output condition being established by predetermined signals at the second outputs of said first and second bistable means.
Claim 7
Dependent Claim
44 words
Apparatus according to claim 3 wherein said second control means comprises an AND gate means responsive to predetermined signals appearing at the second outputs of said first and second bistable means, said AND gate means having an output connected to said read/write control means.
Claim 8
Dependent Claim
49 words
Apparatus according to claim 3 wherein said cycle means comprises AND gate means responsive to predetermined signals appearing at the first output of said first bistable means and at the second output of said second bistable means, and timer means connected to the output of said AND gate means.
Claim 9
Dependent Claim
42 words
Apparatus according to claim 5 further including EXCLUSIVE-OR gate means having an OR input connected to said selectable means and having an EXCLUSIVE input connected to said timer means, said EXCLUSIVE-OR gate means having an output adapted to condition said address rEgister.
Claim 10
Dependent Claim
46 words
Apparatus according to claim 5 wherein said first gate means comprises AND-NOT gate means having an AND input con-nected to said address register and responsive to an address in the maximum position of said address register and having a NOT input connected to said timer means.
Claim 11
Dependent Claim
55 words
Apparatus according to claim 6 further including AND-NOT gate means having an AND input connected to the output of said EXCLUSIVE-OR gate means and having a NOT input connected to the first output of said second bistable means, said AND gate means having an output connected to the first address position of said address register.
Claim 12
Dependent Claim
45 words
Apparatus according to claim 8 wherein said second control means comprises second AND gate means responsive to predetermined signals appearing at the second outputs of said first and second bistable means, said second AND gate means having an output connected to said read/write control means.
Claim 13
Dependent Claim
47 words
Apparatus according to claim 8 wherein said first gate means comprises second AND-NOT gate means having an AND in-put connected to said address register and responsive to an address in the maximum position of said address register and having a NOT input connected to said timer means.
Claim 14
Dependent Claim
46 words
Apparatus according to claim 1 wherein said selectable means comprises latch means capable of providing first and second output signals, first and second switch means connected to said latch means for conditioning said latch means to provide a respective one of said first and second signals.
Claim 15
Dependent Claim
62 words
Apparatus according to claim 11 further including a data register connected to said data lines, said data generator means being adapted to establish said predetermined program of data information in said data register, and complement means responsive to said first output condition of said first control means for establishing the complement of said predetermined program of data information in said data register.
Claim 16
Dependent Claim
243 words
Apparatus according to claim 11 wherein said first control means comprises first and second bistable means each having a set input, a reset input, a first output and a second output, each of said first and second bistable means being responsive to a predetermined signal at its respective set input to discontinue a predetermined signal established at one of its outputs and to establish a predetermined signal at the other of its outputs, each of said first and second bistable means being further responsive to a predetermined signal at its respective reset input to discontinue any predetermined signal established at its second output and to establish a predetermined signal at its first output, the reset inputs of each of said first and second bistable means being connected to said selectable means, the second output of said first bistable means being connected to the set input of said second bistable means, first gate means connected to said address register for establishing a predetermined signal at the set input of said first bistable means, said first output condition of said first control means being established by predetermined signal at the first output of said second bistable means, said second output condition being established by predetermined signals at the first output of said first bistable means and the second output of said second bistable means, and the third output condition being established by predetermined signals at the second outputs of said first and second bistable means.
Claim 17
Dependent Claim
44 words
Apparatus according to claim 13 wherein said second control means comprises an AND gate means responsive to predetermined signals appearing at the second outputs of said first and second bistable means, said AND gate means having an output connected to said read/write control means.
Claim 18
Dependent Claim
49 words
Apparatus according to claim 13 wherein said cycle means comprises AND gate means responsive to predetermined signals appearing at the first output of said first bistable means and at the second output of said second bistable means, and timer means coNnected to the output of said AND gate means.
Claim 19
Dependent Claim
42 words
Apparatus according to claim 15 further including EXCLUSIVE-OR gate means having an OR input connected to said selectable means and having an EXCLUSIVE input connected to said timer means, said EXCLUSIVE-OR gate means having an output adapted to condition said address register.
Claim 20
Dependent Claim
46 words
Apparatus according to claim 15 wherein said first gate means comprises AND-NOT gate means having an AND input connected to said address register and responsive to an address in the maximum position of said address register and having a NOT input connected to said timer means.
Claim 21
Dependent Claim
55 words
Apparatus according to claim 16 further including AND-NOT gate means having an AND input connected to the output of said EXCLUSIVE-OR gate means and having a NOT input connected to the first output of said second bistable means, said AND gate means having an output connected to the first address position of said address register.
Claim 22
Dependent Claim
36 words
Apparatus according to claim 1 wherein said analyzer includes first and second address registers, and third control means for incrementing access to said first address register upon each cycle of access to said second address register.
Claim 23
Dependent Claim
151 words
Apparatus according to claim 19 wherein said third control means comprises bistable means having first and second outputs connected to said first and second address registers, respectively, first AND gate means connected to a first input of said bistable means to condition said bistable means to provide a signal at its first output and second AND gate means connected to a second input of said bistable means to condition said bistable means to provide a signal at its second output, switch means having an output connected to a first input of each of said first and second AND gate means, maximum position sensing means for sensing the completion of a cycle of access to said second address register, said first AND gate means having a second input connected to said sensing means and said second AND gate means having a second input connected to the second output of said bistable means.
Claim 24
Dependent Claim
58 words
Apparatus according to claim 20 further including AND-NOT gate means having its AND input connected to the second output of said bistable means and having its NOT input connected to said sensing means, the output of said AND-NOT gate means being connected to said second address register and to said second input of said second AND gate means.
Claim 25
Dependent Claim
205 words
In a memory analyzer for analyzing the operability of a memory system for a computer, which memory system has a plurality of address and data lines, said analyzer having first and second address registers connected to said address lines, the improvement comprising control means for incrementing access to said first address register upon each cycle of access to said second address register, said control means comprising bistable means having first and second outputs connected to said first and second address registers, respectively, first AND gate means connected to a first input of said bistable means to condition said bistable means to provide a signal at its first output and second AND gate means connected to a second input of said bistable means to condition said bistable means to provide a signal at its second output, switch means having an output connected to a first input of each of said first and second AND gate means, position sensing means for sensing the completion of a cycle of access to said second address register, said first AND gate means having a second input connected to said sensing means and said second AND gate means having a second input connected to the second output of said bistable means.
Claim 26
Dependent Claim
205 words
In a memory analyzer for analyzing the operability of a memory system for a computer, which memory system has a plurality of address and data lines, said analyzer having first and second address registers connected to said address lines, the improvement comprising control means for incrementing access to said first address register upon each cycle of access to said second address register, said control means comprising bistable means having first and second outputs connected to said first and second address registers, respectively, first AND gate means connected to a first input of said bistable means to condition said bistable means to provide a signal at its first output and second AND gate means connected to a second input of said bistable means to condition said bistable means to provide a signal at its second output, switch means having an output connected to a first input of each of said first and second AND gate means, position sensing means for sensing the completion of a cycle of access to said second address register, said first AND gate means having a second input connected to said sensing means and said second AND gate means having a second input connected to the second output of said bistable means.
References Cited (Backward Citations)
US3340513A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-05 | 1976-09-04 | 1977-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-05 | 1980-09-04 | 1981-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-05 | 1984-09-04 | 1985-03-06 | $7700.00 | Window Closed / Lapsed |