Circuit arrangement for telecommunications systems, particularly telephone switching systems, having data protection by way of parity bits

Claim 1

In a circuit arrangement of the type in which a dynamic memory for storing a plurality of informations is connected to a data bus via a first buffer which receives and stores a multibit information and stores the same in the dynamic memory upon receipt of a write instruction and is connected to the data bus via a second buffer and emits information thereto in a chronologically limited manner upon receipt of and only for the duration of a read instruction, the improvement wherein: said second buffer includes a parity bit output; and a parity evaluator is provided and forms a first parity bit and stores the same with the information in the dynamic memory for each incoming information in the first buffer, said parity evaluator derives a second parity bit upon reading of an information from the dynamic memory and comprises comparison means for comparing the first and second parity bits for equality, said parity evaluator connected to the data bus in parallel with the first and second buffers to receive both incoming and outgoing information at the respective times of receipt and transmission and is connected to said parity bit output of the second buffer for receiving the second parity bit upon intermediate storage in the second buffer, whereby, upon each emission of an information, the comparison means of said parity evaluator receives, on the one hand, the second parity bit derived by the parity evaluator and, on the other hand, the first parity bit correspondingly stored in the dynamic memory and output therefrom to the second buffer with the information, and extracted at said parity bit output of the second buffer.