Parity generation and bus matching arrangement for synchronized duplicated data processing units

Claim 2

A diagnostic arrangement for use with a pair of duplicated processing units operating in synchronism, each of said units including an output bus connected to a memory, one of said output buses connectd to said memory via an address register, said arrangement comprising a first parity network providing a first parity indication over the contents of said address register, a second parity network providing a second parity indication over information on the other of said output buses, means for combining said first and second parity indications to generate a combined parity indication, means responsive to said combining means and to the loading by one of said processing units via said one output bus of said address register with an address identifying a storage location in said memory for providing a bus mismatch signal if said first and second parity indications do not match, and means responsive to the loading by said processing units of said output buses with data to be written in said memory and to said combining means for storing in said memory both said combined parity indication and said data, whereby said combined parity indication now indicates parity over said data and over the address in said address register.

Claim 3

The arrangement of claim 1 wherein said processing units also include an input bus for receiving data retrieved from said memory and wherein a parity lead is provided to indicate a parity indication retrieved from said memory along with said data, said retrieved parity indication indicating parity over said retrieved data and address at which said retrieved data was stored, said arrangement further comprising means for applying said read data to said units via said input bus, means in each of said units for gating said read data from said input bus onto its respective output bus, and means for comparing said retrieved parity indication on said parity lead with said combined indication and for generating an error signal if a parity mismatch is detected.

Claim 4

In a data processing system comprising a pair of duplicated processing units operating synchronously but independently and each connected to a respective output bus over which data and address information is communicated to peripheral circuits including a memory, and a peripheral address register connected to one of said units via one of said output buses; a diagnostic and parity generation arrangement comprising a first parity generator providing a first parity indication over the contents of said peripheral address register. a seond parity generator providing a second parity indication over the information on the other one of said output buses, means for combining said first and second parity indications to generate a combined parity indication, means responsive to said combined parity indication and to the loading of said peripheral address register with said address via said one output bus for generating a bus mismatch signal if said first and second parity indications do not match, and means responsive to the application to said output buses by said processing untis of data destined for said memory for storing in said memory both said combined parity indication and said data whereby said stored parity indication indicates parity over said address and over said data.

Claim 5

In a data processing system comprising a pair of duplicated processing units operating synchronously but independently and each connected to a respective output bus over which data and address information is communicated to peripheral circuits including a memory, and a peripheral address register connected to one of said units via one of said output buses; a diagnostic and parity generation arrangement comprising a first parity generator providing a first parity indication over the contents of said peripheral address register. a seond parity generator providing a second parity indication over the information on the other one of said output buses, means for combining said first and second parity indications to generate a combined parity indication, means responsive to said combined parity indication and to the loading of said peripheral address register with said address via said one output bus for generating a bus mismatch signal if said first and second parity indications do not match, and means responsive to the application to said output buses by said processing untis of data destined for said memory for storing in said memory both said combined parity indication and said data whereby said stored parity indication indicates parity over said address and over said data.

Claim 6

In the data processing system of claim 3 wherein parity indicia and data retrieved from said memory are respectively applied to a parity lead and to an input bus connected to each of said units, said diagnostic and parity generation arrangement further comprising means in each of said units operable to gate said retrieved data from said input bus onto the output bus connected to said each unit, and means for comparing said retrieved parity indicia with said combined parity indication and for generating an error signal if a mismatch is detected.

Claim 7

For use in a duplicated microprocessing system comprising a first data manipulation unit comprising a plurality of registers and logic circuits, and connected to a first output bus to convey information via a peripheral address register to a first memory and also connected to an input bus to receive information from said first memory, a second data manipulation unit comprising a plurality of registers and logic circuits, and connected to a second output bus to convey information to said first memory and also connected to an input bus to receive information from said first memory, a second memory storing a plurality of program instructions, and each of said units responsive to program instructions retrieved from said second memory and each executing said retrieved program instructions to control the flow of information between said registers and logic circuits therein, and a selected one of said units also controlling the flow of information between said units and said first memory and said units operating in synchronism and each applying an address and then data to its respective output bus; a diagnostic and parity generation arrangement comprising a first parity generator providing a first parity indication over the contents of said peripheral address register, a second parity generator providing a second parity indication over the instant information on said second output bus, means for combining said first and second parity indicaions to generate a combined parity indication, means responsive to the loading of said address from said first output bus into said peripheral address register and to said combined parity indication for generating a bus mismatch signal if said first and second parity indications do not match, and means for applying said combined parity indication to said first memory for storage therein with said data, wherein when said data is applied to said buses said combined parity indication indicates parity over said data and said address.

Claim 8

For use in a duplicated microprocessing system comprising a first data manipulation unit comprising a plurality of registers and logic circuits, and connected to a first output bus to convey information via a peripheral address register to a first memory and also connected to an input bus to receive information from said first memory, a second data manipulation unit comprising a plurality of registers and logic circuits, and connected to a second output bus to convey information to said first memory and also connected to an input bus to receive information from said first memory, a second memory storing a plurality of program instructions, and each of said units responsive to program instructions retrieved from said second memory and each executing said retrieved program instructions to control the flow of information between said registers and logic circuits therein, and a selected one of said units also controlling the flow of information between said units and said first memory and said units operating in synchronism and each applying an address and then data to its respective output bus; a diagnostic and parity generation arrangement comprising a first parity generator providing a first parity indication over the contents of said peripheral address register, a second parity generator providing a second parity indication over the instant information on said second output bus, means for combining said first and second parity indicaions to generate a combined parity indication, means responsive to the loading of said address from said first output bus into said peripheral address register and to said combined parity indication for generating a bus mismatch signal if said first and second parity indications do not match, and means for applying said combined parity indication to said first memory for storage therein with said data, wherein when said data is applied to said buses said combined parity indication indicates parity over said data and said address.

Claim 9

For use with a pair of processing units, one of said units connected to an address register via a first output bus, and the other of said units receiving data retrieved from a memory via an input bus and applying data to be stored in said memory via a second output bus, said memory having a plurality of discrete addressable locations each adapted to store a data word and a parity bit over said data word and over the address identifying the location at which said data word is stored, said memory responsive to address information in said address register for retrieving both the data word and the parity bit stored at the memory location identified by said address information and for applying said retrieved data to said input bus; a diagnostic arrangement comprising first parity generator means connected to said address register for generating a first parity indication over said address information therein, control means including said other unit for gating said retrieved data word from said input bus onto said second output bus,

Claim 10

For use with a pair of processing units, one of said units connected to an address register via a first output bus, and the other of said units receiving data retrieved from a memory via an input bus and applying data to be stored in said memory via a second output bus, said memory having a plurality of discrete addressable locations each adapted to store a data word and a parity bit over said data word and over the address identifying the location at which said data word is stored, said memory responsive to address information in said address register for retrieving both the data word and the parity bit stored at the memory location identified by said address information and for applying said retrieved data to said input bus; a diagnostic arrangement comprising first parity generator means connected to said address register for generating a first parity indication over said address information therein, control means including said other unit for gating said retrieved data word from said input bus onto said second output bus,

Claim 11

second parity generator means connected to said second output bus for generating a second parity indication over said retrieved data word thereon, logic means for combining said first and second parity indications and for generating a combined parity indication, and

Claim 12

second parity generator means connected to said second output bus for generating a second parity indication over said retrieved data word thereon, logic means for combining said first and second parity indications and for generating a combined parity indication, and

Claim 13

means for comparing said combined parity indication with said retrieved parity bit and for generating an error signal if a mismatch is detected.

Claim 14

means for comparing said combined parity indication with said retrieved parity bit and for generating an error signal if a mismatch is detected.

Claim 15

In a data processing system comprising a pair of processing units operating independently but synchronously to apply an address to first and second output buses respectively and then to apply data to said first and second buses respectively; a register for storing an address applied to said first bus; a memory for storing, at the address in said register, the data on said second bus and a parity bit over said data and said address; a diagnostic and parity generation arrangement comprising a first parity generator providing a first parity indication over said address in said register; a second parity generator proiding a second parity indication over the instant information on said second bus; combining means for combining said first and second parity indications to generate a combined parity indication; means responsive to said combining means and to the loading of said address in said register by one of said processing units for generating an error signal if said parity indications do not match; and means for applying said combined parity indication to said memory, wherein when said data is applied to said buses said combined parity indication represents the parity bit over said data and said address.

Claim 16

In a data processing system comprising a pair of processing units operating independently but synchronously to apply an address to first and second output buses respectively and then to apply data to said first and second buses respectively; a register for storing an address applied to said first bus; a memory for storing, at the address in said register, the data on said second bus and a parity bit over said data and said address; a diagnostic and parity generation arrangement comprising a first parity generator providing a first parity indication over said address in said register; a second parity generator proiding a second parity indication over the instant information on said second bus; combining means for combining said first and second parity indications to generate a combined parity indication; means responsive to said combining means and to the loading of said address in said register by one of said processing units for generating an error signal if said parity indications do not match; and means for applying said combined parity indication to said memory, wherein when said data is applied to said buses said combined parity indication represents the parity bit over said data and said address.