Memory system with error storage

Claim 2

In a memory system including a random access memory array (RAM) organized so that bits are read-out internally a group at a time and where the parity of each such group of bits read-out internally is checked and where there is selected for external read-out from any group of internally read-out bits, a sub-group of less than all of the bits in said group and where less than a whole group of new data bits is written into the memory at any one time, and each time a new data bit is written into a group a new parity bit is generated for that group whereby an error originally present within the group of bits may be masked, the improvement comprising: means for sensing the presence of a parity error in any one of said group of bits being read-out internally when its parity is checked and for producing an error signal corresponding to each group of bits having a parity error; and means for storing each error signal and for subsequently producing, until said means for storing is reset, a parity error signal indication each time a group of bits, corresponding to which an error signal was one produced, is read out.

Claim 3

The improvement as claimed in claim 1 wherein said means for sensing the presence of an error includes a parity checker coupled to said RAM for producing said error signal indicating whether the parity of the bits of a group is in error, and wherein said means for storing comprises a memory array.

Claim 4

In the memory system as claimed in claim 1 wherein said memory array and said means for sensing the presence of an error and then storing that error are formed on the same integrated circuit.

Claim 5

In the memory system is claimed in claim 3 wherein said means for storing an error includes a latch array having a bit location corresponding to each one of said group of bits of said memory array.

Claim 6

A memory module comprising: a memory array of R·C memory cells partitioned internally into W internal words of L bits and organized externally as a memory of X words by Y bits, where L is greater than Y and R·C=W·L=X·Y; and where R, C, W, L, X and Y are integers; means for reading-out a selected Y bits and for concurrently reading the internal word in which the selected Y bits are included; a parity array for storing a parity bit corresponding to each internal word; parity check means receptive of a selected internal word and its corresponding parity bit for ascertaining whether its parity is correct and for producing a first signal indicative thereof; parity error storing means, coupled to said parity check means, having W bit locations, one bit location per internal word, each one of said bit locations of said parity error storing means for permanently storing the occurrence of a parity error in its corresponding internal word; and means, coupled to said parity error storing means for subsequently producing a parity error signal indication each time an internal words is selected whose corresponding bit location in said parity error storing means is storing the previous occurrence of a parity error.

Claim 7

A memory module comprising: a memory array of R·C memory cells partitioned internally into W internal words of L bits and organized externally as a memory of X words by Y bits, where L is greater than Y and R·C=W·L=X·Y; and where R, C, W, L, X and Y are integers; means for reading-out a selected Y bits and for concurrently reading the internal word in which the selected Y bits are included; a parity array for storing a parity bit corresponding to each internal word; parity check means receptive of a selected internal word and its corresponding parity bit for ascertaining whether its parity is correct and for producing a first signal indicative thereof; parity error storing means, coupled to said parity check means, having W bit locations, one bit location per internal word, each one of said bit locations of said parity error storing means for permanently storing the occurrence of a parity error in its corresponding internal word; and means, coupled to said parity error storing means for subsequently producing a parity error signal indication each time an internal words is selected whose corresponding bit location in said parity error storing means is storing the previous occurrence of a parity error.

Claim 8

The memory module as claimed in claim 5 wherein said parity error storing means is an array of storage elements containing one storage element corresponding to each internal word; each storage element normally storing a no error signal condition and being settable to an error signal storing condition when the first signal of its corresponding internal word indicates the presence of a parity error in that internal word.

Claim 9

An integrated circuit suitable for use in a memory system comprising: a random access memory (RAM) array having R·C bit locations arranged in R rows and C columns, said RAM being organized into W "internal" words of L bits each; where W·L is equal to R·C and where R, C, W and L are digits greater than 1; a parity array section of W bits for storing a parity bit for each one of said W "internal" words of said RAM; decoding means coupled to said RAM for selectively reading one of said "internal" words and for concurrently reading-out a data bit out of the L bits of said selected one of said internal words; parity checking means, coupled to said decoding means and to said parity array responsive to the parity of the L bits of the selected internal word and to its parity bit for producing a first level output signal having a first value to indicate the absence of a match (error) between the parity of the L bits and the stored parity bit and having a second value to indicate the presence of a match (no error); a latching array having "N" bit locations where N is an integer equal to or greater than 1, each bit location normally storing one binary value indicating no error and being settable to the other binary condition indicative of error; and means coupled between said parity checking means and said latching array receptive of said first level output setting a bit location in said latching array to said other binary condition when said first level output signal indicates the absence of a match (error).

Claim 10

An integrated circuit suitable for use in a memory system comprising: a random access memory (RAM) array having R·C bit locations arranged in R rows and C columns, said RAM being organized into W "internal" words of L bits each; where W·L is equal to R·C and where R, C, W and L are digits greater than 1; a parity array section of W bits for storing a parity bit for each one of said W "internal" words of said RAM; decoding means coupled to said RAM for selectively reading one of said "internal" words and for concurrently reading-out a data bit out of the L bits of said selected one of said internal words; parity checking means, coupled to said decoding means and to said parity array responsive to the parity of the L bits of the selected internal word and to its parity bit for producing a first level output signal having a first value to indicate the absence of a match (error) between the parity of the L bits and the stored parity bit and having a second value to indicate the presence of a match (no error); a latching array having "N" bit locations where N is an integer equal to or greater than 1, each bit location normally storing one binary value indicating no error and being settable to the other binary condition indicative of error; and means coupled between said parity checking means and said latching array receptive of said first level output setting a bit location in said latching array to said other binary condition when said first level output signal indicates the absence of a match (error).

Claim 11

The combination as claimed in claim 7 wherein said latching array includes W bit locations, one location for each one of said W internal words.

Claim 12

The combination as claimed in claim 8 wherein said latching array includes a static storage cell at each one of its W bit locations.

Claim 13

The combination as claimed in claim 9 wherein each one of said static storage cells of said latching array once set to a condition indicative of the absence of a match remains set to that condition.

Claim 14

A memory system comprising, in combination: a memory array for storing groups of information bits and their parity bits; means responsive to an address for reading from the memory array a selected group of said bits, said group containing information bits having a bit of interest, and a parity bit; means for checking the parity of the selected group of said bits and if there is an error, producing and storing an error bit; means responsive to an address for writing a bit into said array, in a selected bit position in said array, said selected bit position being within a particular group of bits in said array; means for generating a new parity bit for each group of bits each time a bit is written into a bit position of that group of bits for storing that new parity bit in said memory array, whereby whether or not there is an error in a group of bits in a bit position other than the one into which a bit is written, the new parity bit will indicate that the parity for that group of bits is correct whereas there may be an error in said group of bits; and means responsive to the detection of an error in a particular bit position of a selected group of bits read from said memory array and to a stored error bit for that selected group of bits, for automatically correcting said error.

Claim 15

A memory system comprising, in combination: a memory array for storing groups of information bits and their parity bits; means responsive to an address for reading from the memory array a selected group of said bits, said group containing information bits having a bit of interest, and a parity bit; means for checking the parity of the selected group of said bits and if there is an error, producing and storing an error bit; means responsive to an address for writing a bit into said array, in a selected bit position in said array, said selected bit position being within a particular group of bits in said array; means for generating a new parity bit for each group of bits each time a bit is written into a bit position of that group of bits for storing that new parity bit in said memory array, whereby whether or not there is an error in a group of bits in a bit position other than the one into which a bit is written, the new parity bit will indicate that the parity for that group of bits is correct whereas there may be an error in said group of bits; and means responsive to the detection of an error in a particular bit position of a selected group of bits read from said memory array and to a stored error bit for that selected group of bits, for automatically correcting said error.