EP0655741A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory device and serial-parallel data transform circuit
Assignee: Toshiba Corp
•
Filing: 1994-11-29
•
Granted: —
•
Expires: 2014-11-29
Abstract
Abstract In DRAM, a part of data in a row are rewritten at high speed. The memory device comprises dynamic type cell blocks (11); sense amplifiers (3) for sensing data of the cell blocks (11); latches (2) for storing data; data transfer gates for transferring data between the sense amplifiers (3) and the latches(2); and byte write mask circuit blocks (1) for controlling only the data transfer gates corresponding to only the latches (2) in which data have been written, to transfer data to the sense amplifiers (3). The byte write mask circuit block (1) opens only the transfer gates corresponding to the latches (2) to which data are written and further transfer data from the latches (2) to the sense amplifiers (3). Therefore, when data are required to be written in the cell blocks 11, since only the necessary data are written in the latches (2), it is possible to eliminate wasteful data write to the latches (2), thus enabling a high speed data transfer to the cell blocks (11). <IMAGE>
Inventors
- 👤 Haruki Toda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/1006; G11C7/1078
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
169 words
A memory device comprising: at least one memory block (11) having a plurality of memory cells arranged into roughly a matrix pattern, a column group being formed by a predetermined number of columns; a plurality of sense amplifiers (3) each provided for each of the columns; a plurality of latches (2) each provided for each of said sense amplifiers (3), data being transferred between each of said latches (2) and corresponding each of said sense amplifiers (3), a latch group being formed by a predetermined number of said latches (2), the latch group corresponding one-to-one to the column group; a column decoder (9) for outputting a column group select signal (CSL) to select a predetermined number of the latch groups, external data being written only in the selected latch groups; and a plurality of write mask circuits (1) each for storing the latch groups in which data have been written and for enabling data written in the selected latch groups to be transferred to said corresponding sense amplifiers (3).
Claim 2
Dependent Claim
70 words
The memory device of claim 1, wherein a transfer gate (T) is connected between each of said sense amplifiers (3) and each of said latches (2), a transfer gate group being formed by a predetermined number of the transfer gates (T), each of the transfer gate groups corresponding to each of the latch groups, and each of said write mask circuit (1) turning on/off each of said transfer gate groups.
Claim 3
Dependent Claim
96 words
The memory device of claim 1 or 2, wherein each of said latches (2) is connected to each of data lines (4) to transfer data to and from the outside, gating means (G) being connected between each of said latches (2) and each of the data lines (4) to turn on/off interconnection between each of said latches (2) and each of the data lines (4), a gating means group being formed by a predetermined number of said gating means (G), and each of said gating means group being selectively turned on by said column decoder (9).
Claim 4
Dependent Claim
92 words
The memory device of claim 1 or 2, which further comprise plural column group simultaneous accessing means (8) for receiving the column group select signal given by said column decoder (9) and for outputting another select signal to select a predetermined number of column groups adjacent to the column group corresponding to the received column group select signal, so that whenever the column group select signal for selecting a column group is outputted by said column decoder, a predetermined number of column groups adjacent to the selected column group being accessed simultaneously.
Claim 5
Dependent Claim
56 words
The memory device of claim 1, wherein when receiving the column group select signal (CSL) given by said column decoder (9), said plural column group simultaneous accessing means (8) selects one column group adjacent to the column group corresponding to the received column group select signal (CSL) to enable simultaneous access to the two column groups.
Claim 6
Dependent Claim
22 words
The memory device of claim 5, wherein said plural column group simultaneous accessing group (8) is a column group pair read decoder.
Claim 7
Dependent Claim
22 words
The memory device of claim 5, wherein said plural column group simultaneous accessing group (8) is a column group pair write decoder.
Claim 8
Dependent Claim
22 words
The memory device of claim 5, wherein said plural column group simultaneous accessing group (8) is a column group pair read/write decoder.
Claim 9
Dependent Claim
169 words
The memory device of claim 1 ,3,4 or 5,wherein said write mask circuit (1) comprises; a first register circuit (RC1), when the latch group corresponding thereto is selected and thereby data are written, for storing the selection at a selected time point; a second register circuit (RC2) connected in series to said first register circuit (CR1) via a switching element (26), for storing the information stored in said first register (RC1) as information for generating a signal for controlling the transfer gate (T); when data is transferred from said latch (2) to said sense amplifier (3), the switching element (26) being turned off to disconnect said first register circuit (CR1) from said second register circuit (CR2), while keeping the selection of the latch group under this disconnected status stored in said first register circuit; and data stored in said first register circuit (CR1) immediately before the data transfer being outputted to said second register circuit (CR2) as the information for generating the signal for controlling the transfer gate (T).
Claim 10
Dependent Claim
75 words
The memory device of claim 1,2,3,4 or 5,wherein said memory cell block (11) is arranged in middle of the device; said sense amplifiers (3), said latches (2) and said write mask circuits (1) are arranged in sequence on both sides of said block (11) so as to sandwich said block in symmetrical positional relationship with respect to each other; and said column decoder (9) is arranged outside of one of said write mask circuits (1).
Claim 11
Dependent Claim
66 words
The memory device of claim 10, wherein said two or more memory cell blocks are provided; said column decoder (9) is arranged in middle between said two memory cell blocks (11, 11); and said write mask circuits (1), said latches (2) and said sense amplifiers (3) are arranged in sequence on both sides of said column decoder (9) so as to sandwich said column decoder (9).
Claim 12
Dependent Claim
148 words
A serial-parallel data transforming circuit, comprising: serial data inputting means (4, G) for receiving external serial data; latching means having a plurality of latches (2) for latching each of the serial data, a predetermined number of said latches (2) constituting a plurality of latch groups, respectively for outputting data latched by a plurality of said latches (2) as parallel data therefrom; a plurality of data transfer gates (T) each provided at an output terminal of each of said latches (2); and transfer masking means for selecting any of said latch groups, writing the serial data in the latches of the selected latch group, and turning on said data transfer gates (T) corresponding to the latch group in which data have been written to output the parallel data therefrom while keeping closed said data transfer gates (T) corresponding to the latch group in which data have been not written.
Claim 13
Independent Claim
229 words
A method for writing data to a memory device having a plurality of column lines each having memory cells (MC), a sense amplifier (3), a first gate (T), a latch (2), a second gate (G) and a DQ line (4) connected thereto, comprising: first step of writing data from the DQ line (9) to the latch (2) corresponding to the DQ line (9) by turning on the second gate (G) on the basis of a CSL signal outputted from a column decoder (9) and storing in a mask means (1) column location corresponding to the column line connected to the latch (2) in which the data is written; second step of activating a word line (WL) to transfer data stored in the memory cell (MC) to the column line (BL) connected to the sense amplifier; third step of turning on only the first gate (T) connected to the written latch (2) and not turning on the first gates (T) connected to unwritten latch (2) on the basis of a signal (BX) outputted from the mask means (1); and fourth step of activating the sense amplifier (3), wherein the data from the DQ line (4) is written only in the memory cell (MC) corresponding to the written latch (2) and the data read from the remaining memory calls (MC) are rewritten so as not to destory the data stored therein.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.