US5636174A
Expired / Lapsed
US
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Fast cycle time-low latency dynamic random access memories and systems and methods using the same
Assignee: Intellectual Ventures II LLC
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Filing: 1996-01-11
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Granted: 1997-06-03
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Expires: 2016-01-11
Abstract
Abstract A memory 200 comprising a plurality of rows and columns of memory cells, each column of cells associated with a conductive bitline 301. Memory 200 further includes precharge circuitry 204, 206 for precharging a selected one of the bitlines in response to a received control bit.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:09
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/409; G11C11/4094
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
79 words
A memory comprising: an array of a plurality of columns of memory cells, said plurality of columns being associated with N number of bitlines organized as N/B number of groups of B number of bitlines per group, each of a set of N/B number of subwordlines controlling cells coupled to a corresponding said group of bitlines, N and B being integers greater than zero and not approaching infinity; and precharge circuitry for precharging a selected said group of bitlines.
Claim 2
Dependent Claim
79 words
A memory comprising: an array of a plurality of columns of memory cells, said plurality of columns being associated with N number of bitlines organized as N/B number of groups of B number of bitlines per group, each of a set of N/B number of subwordlines controlling cells coupled to a corresponding said group of bitlines, N and B being integers greater than zero and not approaching infinity; and precharge circuitry for precharging a selected said group of bitlines.
Claim 3
Dependent Claim
21 words
The memory of claim 1 wherein said precharge circuitry is further operable to allow remaining ones of said bitlines to float.
Claim 4
Dependent Claim
18 words
The memory of claim 1 wherein each bitline comprises a pair of half-bitlines arranged in an open-bitline fashion.
Claim 5
Dependent Claim
18 words
The memory of claim 1 wherein each bitline comprises a pair of half-bitlines arranged in a folded-bitline fashion.
Claim 6
Dependent Claim
61 words
The memory of claim 1 wherein said array comprises N number of bitlines comprising N/B number of groups of B number of bitlines each, and wherein each of said rows is associated with N/B number of subwordlines each controlling ones of said cells coupled to a corresponding one of said group of bitlines, N and B being integers greater than zero.
Claim 7
Dependent Claim
15 words
The memory of claim 1 wherein said memory cells comprise dynamic random access memory cells.
Claim 8
Dependent Claim
34 words
The memory of claim 2 and further comprising row decoder circuitry coupled to said subwordlines, said row decoder circuitry activating a selected one of said wordlines corresponding to a precharged group of said bitlines.
Claim 9
Dependent Claim
17 words
The memory of claim 1 and further comprising column decoder circuitry for controlling access to said bitlines.
Claim 10
Dependent Claim
79 words
A memory comprising: an array of memory cells arranged in columns, each column associated with a bitline, access to selected cells of said array controlled with a plurality of sets of subwordlines, wherein each subwordline of each set controls ones of said cells coupled to a corresponding group of said bitlines; precharge circuitry for precharging a selected said group of bitlines; and addressing circuitry for selecting a said subwordline controlling said cells coupled to said selected group of bitlines.
Claim 11
Dependent Claim
79 words
A memory comprising: an array of memory cells arranged in columns, each column associated with a bitline, access to selected cells of said array controlled with a plurality of sets of subwordlines, wherein each subwordline of each set controls ones of said cells coupled to a corresponding group of said bitlines; precharge circuitry for precharging a selected said group of bitlines; and addressing circuitry for selecting a said subwordline controlling said cells coupled to said selected group of bitlines.
Claim 12
Dependent Claim
45 words
The memory of claim 9 wherein said addressing circuitry comprises first row decoder circuitry for controlling selection of said subwordlines of a first set of said rows and second row decoder circuitry for controlling selection of said subwordlines of a second set of said rows.
Claim 13
Dependent Claim
18 words
The memory of claim 9 wherein said addressing circuitry selects a subwordline in response to a row address.
Claim 14
Dependent Claim
15 words
The memory of claim 11 wherein said row address is received during a precharge cycle.
Claim 15
Dependent Claim
42 words
The memory of claim 9 wherein said precharge circuitry comprises precharge decode circuitry for selecting a group of bitlines for precharging and circuitry under the control of said precharge decode circuitry for pulling a selected group of bitlines to a precharge voltage.
Claim 16
Dependent Claim
19 words
The memory of claim 9 wherein said precharge circuitry precharges a selected group of bitlines to a positive voltage.
Claim 17
Dependent Claim
24 words
The memory of claim 9 wherein said precharging circuitry selects a group of bitlines for precharging in response to at least one address bit.
Claim 18
Dependent Claim
27 words
The memory of claim 9 and further comprising column decoder circuitry for selecting ones of said cells coupled to said selected group of bitlines to be accessed.
Claim 19
Dependent Claim
137 words
A memory subsystem comprising: input/output circuitry for inputting and outputting data and addresses; and at least one memory bank coupled to said input/output circuitry comprising: a plurality of columns of memory cells, each cell of a column coupled to a bitline associated with said column and a corresponding one of a plurality of subwordlines; precharge circuitry for precharging selected bitlines to a predetermined voltage; precharge decoder circuitry for selecting in response to precharge select bits selected bitlines for precharge by said precharge circuitry; row decoder circuitry for activating a selected subwordline in response to a received row address to select a set of cells coupled to said selected subwordline for access; and column decoder circuitry for selecting in response to a column address selected bitlines coupled to selected cells of said set of cells to be accessed.
Claim 20
Dependent Claim
137 words
A memory subsystem comprising: input/output circuitry for inputting and outputting data and addresses; and at least one memory bank coupled to said input/output circuitry comprising: a plurality of columns of memory cells, each cell of a column coupled to a bitline associated with said column and a corresponding one of a plurality of subwordlines; precharge circuitry for precharging selected bitlines to a predetermined voltage; precharge decoder circuitry for selecting in response to precharge select bits selected bitlines for precharge by said precharge circuitry; row decoder circuitry for activating a selected subwordline in response to a received row address to select a set of cells coupled to said selected subwordline for access; and column decoder circuitry for selecting in response to a column address selected bitlines coupled to selected cells of said set of cells to be accessed.
Claim 21
Dependent Claim
20 words
The memory subsystem of claim 17 wherein each bitline comprises a pair of complementary half-bitlines arranged in an open-bitline manner.
Claim 22
Dependent Claim
24 words
The memory subsystem of claim 17 wherein each bitline comprises a pair of complementary half-bitlines arranged as a single array in a folded-bitline manner.
Claim 23
Dependent Claim
22 words
The memory subsystem of claim 17 wherein said precharge circuitry precharges selected bitlines during a precharge cycle defined by a clocking signal.
Claim 24
Dependent Claim
15 words
The memory subsystem of claim 20 wherein said clocking signal comprises a row address strobe.
Claim 25
Dependent Claim
23 words
The memory subsystem of claim 20 wherein said input/output circuitry is operable to input received row and column addresses during said precharge cycle.
Claim 26
Dependent Claim
18 words
The memory subsystem of claim 22 wherein said precharge select bits comprises a portion of a column address.
Claim 27
Dependent Claim
30 words
The memory subsystem of claim 17 wherein said at least one bank comprises a plurality of banks, one of said banks selected for access in response to bank select bit.
Claim 28
Dependent Claim
34 words
The memory subsystem of claim 17 wherein said input/output circuitry comprises multiplexed address/data pins for receiving address bits during said precharge cycle and for exchanging data with said column decoder during an active cycle.
Claim 29
Independent Claim
162 words
A method of operating a memory including a plurality of memory cells arranged in columns, the cells of a column coupled to a bitline associated with the column and each cell coupled to a preselected one of a plurality of subwordlines, precharge circuitry for procharging a selected group of bitlines in response to at least one precharge select bit, and addressing circuitry for activating a selected one of the subwordlines in response to an address, the method comprising the steps of: during a precharge period, providing at least one precharge select bit for procharging a selected group of bitlines; during the precharge period, providing a row address for selecting a subwordline for activation, the subwordline selected for activation controlling cells coupled to the group of bitlines selected for precharge; during the precharge period, precharging the selected group of bitlines; and during an active cycle, accessing at least some of the cells coupled to a subwordline selected for activation during the precharge period.
Claim 30
Independent Claim
162 words
A method of operating a memory including a plurality of memory cells arranged in columns, the cells of a column coupled to a bitline associated with the column and each cell coupled to a preselected one of a plurality of subwordlines, precharge circuitry for procharging a selected group of bitlines in response to at least one precharge select bit, and addressing circuitry for activating a selected one of the subwordlines in response to an address, the method comprising the steps of: during a precharge period, providing at least one precharge select bit for procharging a selected group of bitlines; during the precharge period, providing a row address for selecting a subwordline for activation, the subwordline selected for activation controlling cells coupled to the group of bitlines selected for precharge; during the precharge period, precharging the selected group of bitlines; and during an active cycle, accessing at least some of the cells coupled to a subwordline selected for activation during the precharge period.
Claim 31
Dependent Claim
22 words
The method of claim 26 and further including the step of timing the precharge period and the active cycle with a clock.
Claim 32
Dependent Claim
25 words
The method of claim 26 and further including the step of timing the precharge period and the active cycle with a row address column strobe.
Claim 33
Dependent Claim
26 words
The method of claim 26 wherein said step of providing the address comprises the step of providing the address to at least one multiplexed address/data pin.
Claim 34
Dependent Claim
27 words
The method of claim 29 wherein said step of accessing comprises the step of accessing at least one cell through the at least one multiplexed address/data pin.
Claim 35
Dependent Claim
23 words
The method of claim 26 and further comprising the step of selecting the cells for access in response to a received column address.
Claim 36
Dependent Claim
18 words
The method of claim 26 wherein a column address is received prior to receipt of a row address.
Claim 37
Dependent Claim
17 words
The method of claim 26 wherein the precharge select bit comprises a part of the column address.
Claim 38
Dependent Claim
30 words
The method of claim 31 wherein said step of selecting cells for access comprises the step of preforming a page mode access in response to a plurality of column addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |