US5408129A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit I/O using a high performance bus interface
Assignee: Rambus Inc
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Filing: 1994-01-18
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Granted: 1995-04-18
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Expires: 2014-01-18
Abstract
Abstract The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:52
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
330 words
A packaged integrated circuit, comprising: (A) a semiconductor die having an integrated circuitry and a plurality of connection pads arranged along a first side of a plurality of sides of the semiconductor die, wherein each of the plurality of connection pads is spaced at a predetermined distance with another one of the plurality of connection pads, wherein the plurality of connection pads are connected to the integrated circuitry, wherein the semiconductor die only includes the plurality of connection pads that are only arranged on the first side of the semiconductor die and no connection pad is provided along other sides of the plurality of sides of the semiconductor die; (B) a package for packaging the semiconductor die; (C) a plurality of pins mounted along a first side of a plurality of sides of the package for providing coupling to external bus lines for the integrated circuitry, wherein the plurality of pins are only mounted on the first side of the package and no pin is provided along other sides of the plurality of sides of the package, wherein the distance between any two of the plurality of pins is substantially equal to the predetermined distance between any two of the plurality of connection pads; (D) a plurality of wires for coupling the plurality of connection pads to the plurality of pins, wherein when the semiconductor die is packaged inside the package, the first side of the package faces the first side of the semiconductor die such that (1) each of the plurality of pins faces one of the plurality of connection pads and (2) each of the plurality of wires that connects one of the plurality of pins to one of the plurality of connection pads has an effective lead length that is substantially minimized and substantially equal to the effective lead length of each other one of the plurality of wires, wherein the effective lead length of each of the plurality of wires is approximately less than 4 millimeters.
Claim 2
Dependent Claim
330 words
A packaged integrated circuit, comprising: (A) a semiconductor die having an integrated circuitry and a plurality of connection pads arranged along a first side of a plurality of sides of the semiconductor die, wherein each of the plurality of connection pads is spaced at a predetermined distance with another one of the plurality of connection pads, wherein the plurality of connection pads are connected to the integrated circuitry, wherein the semiconductor die only includes the plurality of connection pads that are only arranged on the first side of the semiconductor die and no connection pad is provided along other sides of the plurality of sides of the semiconductor die; (B) a package for packaging the semiconductor die; (C) a plurality of pins mounted along a first side of a plurality of sides of the package for providing coupling to external bus lines for the integrated circuitry, wherein the plurality of pins are only mounted on the first side of the package and no pin is provided along other sides of the plurality of sides of the package, wherein the distance between any two of the plurality of pins is substantially equal to the predetermined distance between any two of the plurality of connection pads; (D) a plurality of wires for coupling the plurality of connection pads to the plurality of pins, wherein when the semiconductor die is packaged inside the package, the first side of the package faces the first side of the semiconductor die such that (1) each of the plurality of pins faces one of the plurality of connection pads and (2) each of the plurality of wires that connects one of the plurality of pins to one of the plurality of connection pads has an effective lead length that is substantially minimized and substantially equal to the effective lead length of each other one of the plurality of wires, wherein the effective lead length of each of the plurality of wires is approximately less than 4 millimeters.
Claim 3
Dependent Claim
14 words
The packaged integrated circuit of claim 1, wherein the integrated circuitry is a memory.
Claim 4
Dependent Claim
17 words
The packaged integrated circuit of claim 2, wherein the memory is a dynamic random access memory (DRAM).
Claim 5
Dependent Claim
18 words
The packaged integrated circuit of claim 1, wherein the predetermined distance is in a range of 0.2-0.5 millimeters.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |