Packaging for semiconductor logic devices

Claim 1

A memory module for receiving information from, and transferring information to, an electronic device in a plurality of parallel processes, the plurality of parallel processes being addressed as a byte of said information, comprising: a. a wafer section having a substantially planar surface, die attach locations, plural memory arrays, and plural data out signals, with one data out signal corresponding to each memory array; b. a plurality of conductive leads, said leads being self-supporting for connection of said wafer section to an external device without the benefit of supporting encapsulation material, said leads further being electrically coupled with said wafer section die attach locations thereby providing an electrical pathway allowing the transfer of said logic information between said wafer section and the electronic device, said pathway providing channels between said wafer section and the electronic device, said wafer section thereby addressable in byte data segments; and c. said plurality of conductive leads and said wafer section forming a module which has a substantially flat profile, which extends planarly in a direction generally defined by said planar surface of said wafer section.