High density integration of semiconductor circuit

Claim 2

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path including a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, said electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, said semiconductor substrate having first and second main surfaces, opposite to each other in said thickness direction, said conductive member provided in said anisotropic etch pit electrically connecting the first main surface of the semiconductor substrate, where a circuit element is formed, to the second main surface of the semiconductor substrate, said pit being made by a process including the step of boring a hole under a highly-doped layer which is part of said circuit element, from the second main surface of said semiconductor substrate to said highly-doped layer, by an anisotropic etching method, and the electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 3

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction; in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, the insulating board having first and second main surfaces, opposite to each other in the thickness direction, wherein a semiconductor substrate and an insulating board have substantially the same size, wherein the insulating board includes therein a coolant path, said coolant path including a groove, in the insulating board, for passing a coolant therethrough, the groove being provided by walls formed in said insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, said electrical communication paths piercing said semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in said semiconductor substrate, and said electrical communication paths piercing said insulating board including a plurality of conductive portions insulated electrically from each other for providing an electrical connection between the first and second main surfaces of said insulating board, the plurality of conductive portions being provided on the walls, providing the groove, formed in the insulating board.

Claim 4

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction; in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, the insulating board having first and second main surfaces, opposite to each other in the thickness direction, wherein a semiconductor substrate and an insulating board have substantially the same size, wherein the insulating board includes therein a coolant path, said coolant path including a groove, in the insulating board, for passing a coolant therethrough, the groove being provided by walls formed in said insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, said electrical communication paths piercing said semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in said semiconductor substrate, and said electrical communication paths piercing said insulating board including a plurality of conductive portions insulated electrically from each other for providing an electrical connection between the first and second main surfaces of said insulating board, the plurality of conductive portions being provided on the walls, providing the groove, formed in the insulating board.

Claim 5

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner than an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path including a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and said insulating board in the thickness direction, electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, said conductive member provided in said anisotropic etch pit electrically connecting a first main surface, of first and second main surfaces of the semiconductor substrate, where a circuit element is formed, to the second main surface of the semiconductor substrate, said pit being made by a process including the step of boring a hole under a highly-doped layer which is part of said circuit element, from the second main surface of said semiconductor substrate to said highly-doped layer, by an anisotropic etching method, said pit extending from the second main surface of the semiconductor substrate to said highly doped layer without extending entirely through the thickness of the semiconductor substrate, and said conductive member provided in said anisotropic etch pit is in electrical contact with said highly doped layer, the conductive member and highly doped layer providing an electrical communication path piercing the semiconductor substrate in the thickness direction, and said electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 6

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner than an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path including a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and said insulating board in the thickness direction, electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, said conductive member provided in said anisotropic etch pit electrically connecting a first main surface, of first and second main surfaces of the semiconductor substrate, where a circuit element is formed, to the second main surface of the semiconductor substrate, said pit being made by a process including the step of boring a hole under a highly-doped layer which is part of said circuit element, from the second main surface of said semiconductor substrate to said highly-doped layer, by an anisotropic etching method, said pit extending from the second main surface of the semiconductor substrate to said highly doped layer without extending entirely through the thickness of the semiconductor substrate, and said conductive member provided in said anisotropic etch pit is in electrical contact with said highly doped layer, the conductive member and highly doped layer providing an electrical communication path piercing the semiconductor substrate in the thickness direction, and said electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 7

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path includes a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, said electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, the semiconductor substrates each having upper and lower main surfaces opposite to each other in the thickness direction, and the plurality of electrical communication paths which pierce the semiconductor substrate in the direction of the thickness thereof extending from the upper main surface to the lower main surface, and said electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 8

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path includes a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, said electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, the semiconductor substrates each having upper and lower main surfaces opposite to each other in the thickness direction, and the plurality of electrical communication paths which pierce the semiconductor substrate in the direction of the thickness thereof extending from the upper main surface to the lower main surface, and said electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 9

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path including a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction, the electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, the plurality of electrical communication paths which pierce the semiconductor substrate in the thickness direction each including a highly doped layer and the conductive member, the conductive member extending in the pit formed in the semiconductor substrate in the thickness direction thereof, the pit not extending completely through the semiconductor substrate, the conductive member being in electrical contact with said highly doped layer, and said electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 10

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein said insulating board includes a coolant path, in said insulating board, said coolant path including a groove in the insulating board for passing a coolant therethrough, the groove being provided by walls formed in the insulating board; and wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction, the electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, the plurality of electrical communication paths which pierce the semiconductor substrate in the thickness direction each including a highly doped layer and the conductive member, the conductive member extending in the pit formed in the semiconductor substrate in the thickness direction thereof, the pit not extending completely through the semiconductor substrate, the conductive member being in electrical contact with said highly doped layer, and said electrical communication paths piercing the insulating board including conductive portions extending on the walls, providing the groove, formed in the insulating board.

Claim 11

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, the electrical communication path piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, each semiconductor substrate and insulating board having first and second main surfaces opposite to each other in the thickness direction, and the plurality of electrical communication paths piercing the semiconductor substrate in the direction of the thickness thereof extending from the first main surface of the semiconductor substrate to the second main surface thereof, and the electrical communication paths piercing the insulating board including conductive portions; and wherein said insulating board includes electrodes on one of the first and second surfaces of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on one of the first and second surfaces of each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 12

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates, wherein a semiconductor substrate and an insulating board have substantially the same size; wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce said semiconductor substrate and the insulating board in the thickness direction, the electrical communication path piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, each semiconductor substrate and insulating board having first and second main surfaces opposite to each other in the thickness direction, and the plurality of electrical communication paths piercing the semiconductor substrate in the direction of the thickness thereof extending from the first main surface of the semiconductor substrate to the second main surface thereof, and the electrical communication paths piercing the insulating board including conductive portions; and wherein said insulating board includes electrodes on one of the first and second surfaces of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on one of the first and second surfaces of each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 13

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates; wherein a semiconductor substrate and an insulating board have substantially the same size; wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction, the electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, the plurality of electrical communication paths which pierce the semiconductor substrate each including a highly doped layer and the conductive member, the conductive member extending in the pit formed in the semiconductor substrate in the thickness direction, the pit not extending completely through the semiconductor substrate, the conductive member being in electrical contact with said highly-doped layer, and the electrical communication paths piercing the insulating board including conductive portions; and wherein said insulating board includes electrodes on one of the first and second surfaces of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on one of the first and second surfaces of each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 14

An integrated circuit structure formed by stacking a plurality of semiconductor substrates, in a thickness direction, in such a manner that an insulating board is sandwiched between adjacent semiconductor substrates; wherein a semiconductor substrate and an insulating board have substantially the same size; wherein both the semiconductor substrate and the insulating board include a plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction, the electrical communication paths piercing the semiconductor substrate including a conductive member provided in an anisotropic etch pit which is formed in the semiconductor substrate, the plurality of electrical communication paths which pierce the semiconductor substrate each including a highly doped layer and the conductive member, the conductive member extending in the pit formed in the semiconductor substrate in the thickness direction, the pit not extending completely through the semiconductor substrate, the conductive member being in electrical contact with said highly-doped layer, and the electrical communication paths piercing the insulating board including conductive portions; and wherein said insulating board includes electrodes on one of the first and second surfaces of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on one of the first and second surfaces of each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 15

An integrated circuit structure according to claim 5, wherein said conductive member provided in said anisotropic etch pit includes a metal member which has a low melting point and fills up said anisotropic etch pit.

Claim 16

An integrated circuit structure according to claim 1, wherein said coolant path includes a plurality of parallel paths provided at regular intervals.

Claim 17

An integrated circuit structure according to claim 1, wherein both ends of said electrical communication paths piercing said insulating board are different from each other in the shape of cross section.

Claim 18

An integrated circuit structure according to claim 10, wherein said electrical communication paths piercing said insulating board have a first rectangular cross section at one end and has a second rectangular cross section at the other end, and a lengthwise direction of said first rectangular cross section makes an angle with that of said second rectangular cross section.

Claim 19

An integrated circuit structure according to claim 10, wherein said electrical communication paths piercing said insulating board have a rectangular cross section at one end and has a circular cross section at the other end.

Claim 20

An integrated circuit structure according to claim 10, wherein said plurality of electrical communication paths piercing said insulating board are uniform in chemical composition.

Claim 21

An integrated circuit structure according to claim 2, wherein said insulating board includes electrodes which are insulated electrically from each other and connected electrically with said conductive portions, which electrodes are arranged on one of said main surfaces of said insulating board.

Claim 22

An integrated circuit structure according to claim 14, wherein said electrodes of said insulating board, and electrodes formed on each of said semiconductor substrates, make up capacitors when said insulating board and said semiconductor substrate are stacked.

Claim 23

An integrated circuit structure according to claim 2, wherein said insulating board is made of a material which has high thermal conductivity and is electrically insulative.

Claim 24

An insulating board according to claim 2, wherein said insulating board is made of silicon carbide which has high thermal conductivity and is electrically insulative.

Claim 25

An integrated circuit structure according to claim 6, wherein said first and second main surfaces of said semiconductor substrate are substantially parallel to a (100) crystallographic plane.

Claim 26

An integrated circuit structure according to claim 3, wherein said highly-doped layer is doped with boron.

Claim 27

An integrated circuit structure according to claim 3, wherein said highly-doped layer has an impurity concentration of 10 19 cm -3 or more.

Claim 28

An integrated circuit structure according to claim 3, wherein said highly-doped layer is part of one of the source region and drain region of a P-channel MOS transistor.

Claim 29

An integrated circuit structure according to claim 3, further comprising a thick protective film on the second main surface of said semiconductor substrate, said thick protective film having been formed before said hole is bored from the second main surface of said semiconductor substrate.

Claim 30

An integrated circuit structure according to claim 4, wherein the plurality of electrical communication paths which pierce the semiconductor substrate in the thickness direction each include a highly doped layer and the conductive member, the conductive member extending in the pit formed in the semiconductor substrate in the thickness direction, the pit not extending completely through the semiconductor substrate, the conductive member being in electrical contact with said highly doped layer.

Claim 31

An integrated circuit structure according to claim 5, wherein said conductive member fills said pit.

Claim 32

An integrated circuit structure according to claim 24, wherein said conductive member filling said pit is a metal having a low melting point.

Claim 33

An integrated circuit structure according to claim 5, wherein a heat conductive grease is provided between adjacent semiconductor substrates and insulating boards.

Claim 34

An integrated circuit structure according to claim 1, said structure including a plurality of circuit elements provided on one of the plurality of semiconductor substrates, with electrical connections to said plurality of circuit elements being provided by said plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the direction of thickness thereof.

Claim 35

An integrated circuit structure according to claim 27, wherein the plurality of circuit elements provided on said one of the semiconductor substrates are connected electrically by wiring, so as to form an integrated circuit.

Claim 36

An integrated circuit structure according to claim 27, wherein said plurality of circuit elements include CMOS transistor elements.

Claim 37

An integrated circuit structure according to claim 1, wherein the semiconductor substrate is a silicon substrate.

Claim 38

An integrated circuit structure according to claim 2, further comprising a plurality of circuit elements formed on one of the plurality of semiconductor substrates, said plurality of circuit elements being connected by wiring, with further connections to said plurality of circuit elements by way of said plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction.

Claim 39

An integrated circuit structure according to claim 3, further comprising a plurality of circuit elements formed on one of the plurality of semiconductor substrates, said plurality of circuit elements being connected by wiring, with further connections to said plurality of circuit elements by way of said plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction.

Claim 40

An integrated circuit structure according to claim 4, further comprising a plurality of circuit elements formed on one of the plurality of semiconductor substrates, said plurality of circuit elements being connected by wiring, with further connections to said plurality of circuit elements by way of said plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction.

Claim 41

An integrated circuit structure according to claim 5, further comprising a plurality of circuit elements formed on one of the plurality of semiconductor substrates, said plurality of circuit elements being connected by wiring, with further connections to said plurality of circuit elements by way of said plurality of electrical communication paths which respectively pierce the semiconductor substrate and the insulating board in the thickness direction.

Claim 42

An integrated circuit structure according to claim 1, wherein said hole is a hole bored only part way through the thickness direction of the semiconductor substrate, from said second main surface of said semiconductor substrate to said highly-doped layer, and wherein said conductive member is provided in said hole to provide electrical connection from said second main surface of said highly-doped layer.

Claim 43

A integrated circuit structure according to claim 23, wherein said pit, which does not extend completely through the semiconductor substrate, extends to said highly doped layer, the conductive member extending in the pit so as to contact the highly doped layer.

Claim 44

An integrated circuit structure according to claim 36, wherein each said highly doped layer extends in the thickness direction from the upper main surface of the semiconductor substrate toward the lower main surface of the semiconductor substrate, but not completely through the semiconductor substrate in the thickness direction, and each said pit extends from the lower main surface of the semiconductor substrate.

Claim 45

An integrated circuit structure according to claim 1, wherein said insulating board includes electrodes on a surface of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 46

An integrated circuit structure according to claim 3, wherein said insulating board includes electrodes on a surface of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 47

An integrated circuit structure according to claim 4, wherein said insulating board includes electrodes on a surface of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.

Claim 48

An integrated circuit structure according to claim 5, wherein said insulating board includes electrodes on a surface of the insulating board, the electrodes being electrically isolated from each other and respectively connected electrically to said conductive portions; and wherein said electrodes of said insulating board, and electrodes provided on each of the semiconductor substrates, form capacitors when said insulating board and an adjacent semiconductor substrate are stacked.