US5627780A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing a non-volatile memory
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1995-08-24
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Granted: 1997-05-06
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Expires: 2015-08-24
Abstract
Abstract An integrated circuit memory device has: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to the data latches; a set of address latches for holding address bits for addressing the memory array; a test bus; a data bit routing circuit connected to the data latches for selectively routing data bits to either the memory array or the test bus; an address bit routing circuit connected to the address latches for selectively routing address bits to either the array or the test bus; and an output circuit for outputting data bits and address bits on the test bus. In this way, data bits and address bits can be checked for accuracy against the originally supplied data bits and address bits. Thus, a test can be conducted without requiring data actually to be written to memory cells of the memory.
Inventors
- 👤 Vijay Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/02
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
157 words
An integrated circuit memory device comprising: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to said data latches; a set of address latches for holding address bits for addressing said memory array; a plurality of address tracks for supplying address bits to said address latches; a test bus; a data bit routing circuit connected to said data latches for selectively routing data bits to one of said array and said test bus; an address bit routing circuit connected to said address latches for selectively routing address bits to one of said array and said test bus; and output circuitry for outputting data bits and address bits on said test bus whereby said data bits and address bits can be checked for accuracy against data bits and address bits originally supplied via said data tracks and address tracks.
Claim 2
Dependent Claim
157 words
An integrated circuit memory device comprising: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to said data latches; a set of address latches for holding address bits for addressing said memory array; a plurality of address tracks for supplying address bits to said address latches; a test bus; a data bit routing circuit connected to said data latches for selectively routing data bits to one of said array and said test bus; an address bit routing circuit connected to said address latches for selectively routing address bits to one of said array and said test bus; and output circuitry for outputting data bits and address bits on said test bus whereby said data bits and address bits can be checked for accuracy against data bits and address bits originally supplied via said data tracks and address tracks.
Claim 3
Dependent Claim
49 words
An integrated circuit memory device according to claim 1 wherein said data bit routing circuit is connected to selectively supply only a subset of said data bits from said data latches to said test bus, said subset being selected from at least one fast and one slow data track.
Claim 4
Dependent Claim
47 words
An integrated circuit memory device according to claim 1 or 2 wherein the address bit routing circuit is connected to supply only a subset of said address bits selectively to said test bus, said subset being selected from at least one fast and one slow address track.
Claim 5
Dependent Claim
26 words
An integrated circuit memory device according to claim 2 or 3 wherein four data bits and four address bits are selectively routed to said test bus.
Claim 6
Dependent Claim
25 words
An integrated circuit memory device according to claim 1 which includes addressing circuitry connected to receive said address bits and to address said memory array.
Claim 7
Dependent Claim
34 words
An integrated circuit memory device according to claim 1 which includes programming circuitry connected to receive said data bits and to program said memory array in accordance with said data bits at selected addresses.
Claim 8
Dependent Claim
22 words
An integrated circuit memory device according to claim 1 which includes sensing circuitry for reading data bits stored in said memory array.
Claim 9
Dependent Claim
31 words
An integrated circuit memory device according to claim 7 wherein said sense circuitry is connected to an output data bus for supplying data bits read from said memory array off chip.
Claim 10
Dependent Claim
31 words
An integrated circuit memory device according to claim 8 which includes an output switch for selectively connecting said output data bus and said test bus to output pads of the chip.
Claim 11
Dependent Claim
23 words
An integrated circuit memory device according to claim 1 wherein said memory array includes a plurality of single transistor floating gate memory cells.
Claim 12
Independent Claim
86 words
A method of testing an integrated circuit memory device which comprises a memory array, the method comprising the steps of: storing data bits in a set of data latches; storing a set of address bits in a set of address latches; on selection of a test mode, routing data bits from said data latches and address bits from said address latches to a test bus; and comparing said data bits and address bits on said test bus with the originally supplied data bits and address bits.
Claim 13
Independent Claim
86 words
A method of testing an integrated circuit memory device which comprises a memory array, the method comprising the steps of: storing data bits in a set of data latches; storing a set of address bits in a set of address latches; on selection of a test mode, routing data bits from said data latches and address bits from said address latches to a test bus; and comparing said data bits and address bits on said test bus with the originally supplied data bits and address bits.
Claim 14
Dependent Claim
30 words
A method according to claim 11 wherein a subset of said data bits supplied to said data latches is connected to said test bus on selection of said test mode.
Claim 15
Dependent Claim
30 words
A method according to claim 11 or 12 wherein a subset of said address bits supplied to said address latches is connected to said test bus in said test mode.
References Cited (Backward Citations)
US3710350A
Cited
US3961252A
Cited
US3961254A
Cited
EP0012018A1
Cited
US5175840A
Cited
US5287326A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-05 | 2000-11-04 | 2001-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-05 | 2004-11-04 | 2005-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-05 | 2008-11-04 | 2009-05-06 | $7700.00 | Window Closed / Lapsed |