US3961252A
Expired / Lapsed
US
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Testing embedded arrays
Assignee: International Business Machines Corp
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Filing: 1974-12-20
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Granted: 1976-06-01
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Expires: 1994-12-20
Abstract
Abstract An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.
Inventors
- 👤 Edward B. Eichelberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:09
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/3185; G01R31/318533; G01R31/318544; G11; G11C; G11C29/00; G11C29/02; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/20
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
70 words
In the testing of a memory array including address and data registers, the improvement comprising: means for scanning a test pattern into the address and data registers; means for shifting the test pattern through said address and data registers; means converting said registers to counters; feedback means for recirculating said register counter outputs to said address and data register inputs; and, means for testing the output of said memory array.
Claim 2
Dependent Claim
70 words
In the testing of a memory array including address and data registers, the improvement comprising: means for scanning a test pattern into the address and data registers; means for shifting the test pattern through said address and data registers; means converting said registers to counters; feedback means for recirculating said register counter outputs to said address and data register inputs; and, means for testing the output of said memory array.
Claim 3
Dependent Claim
25 words
The invention defined by claim 1 including control means for switching the input to said registers between said register counter outputs and said scanning means.
Claim 4
Dependent Claim
23 words
The invention defined by claim 1 wherein said testing means includes means for comparing the data register counter outputs with the array output.
Claim 5
Dependent Claim
15 words
The invention defined by claim 1 wherein said feedback means includes an EXCLUSIVE OR network.
Claim 6
Dependent Claim
17 words
The invention defined by claim 1 including means for complementing the output of said EXCLUSIVE OR network.
Claim 7
Dependent Claim
110 words
In an LSI semiconductor device comprising a memory array and including address and data registers, associated logic circuitry and primary access points to and from external circuitry, operatively associated and so arranged as to provide no direct access from said primary access points to all portions of said memory array, the improvement comprising: means bypassing said associated logic circuitry for scanning a test pattern into the address and data registers; means for shifting the test pattern through said address and data registers; means converting said registers to counters; feedback means for recirculating said register counter outputs to said address and data register inputs; and, means for testing said array output.
Claim 8
Dependent Claim
110 words
In an LSI semiconductor device comprising a memory array and including address and data registers, associated logic circuitry and primary access points to and from external circuitry, operatively associated and so arranged as to provide no direct access from said primary access points to all portions of said memory array, the improvement comprising: means bypassing said associated logic circuitry for scanning a test pattern into the address and data registers; means for shifting the test pattern through said address and data registers; means converting said registers to counters; feedback means for recirculating said register counter outputs to said address and data register inputs; and, means for testing said array output.
Claim 9
Dependent Claim
25 words
The invention defined by claim 6 including control means for switching the input to said registers between said register counter outputs and said scanning means.
Claim 10
Dependent Claim
23 words
The invention defined by claim 6 wherein said testing means includes means for comparing the data register counter outputs with the array output.
Claim 11
Dependent Claim
15 words
The invention defined by claim 6 wherein said feedback means includes an EXCLUSIVE OR network.
Claim 12
Dependent Claim
17 words
The invention defined by claim 9 including means for complementing the output of said EXCLUSIVE OR network.
Claim 13
Dependent Claim
63 words
In the method of testing a memory array including address and data registers, the improvement comprising; scanning a test pattern into the address and data registers; shifting the test pattern through said address and data registers; converting the registers to counters; feeding the register counter outputs to the address and data inputs; and, comparing the data register counter outputs with the array output.
Claim 14
Dependent Claim
63 words
In the method of testing a memory array including address and data registers, the improvement comprising; scanning a test pattern into the address and data registers; shifting the test pattern through said address and data registers; converting the registers to counters; feeding the register counter outputs to the address and data inputs; and, comparing the data register counter outputs with the array output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-01 | 1979-12-01 | 1980-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-01 | 1983-12-01 | 1984-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-01 | 1987-12-01 | 1988-06-01 | $7700.00 | Window Closed / Lapsed |