US5457407A
Expired / Lapsed
US
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Binary weighted reference circuit for a variable impedance output buffer
Assignee: Sony Electronics Inc
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Filing: 1994-07-06
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Granted: 1995-10-10
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Expires: 2014-07-06
Abstract
Abstract An output buffer comprises a reference circuit having a plurality of reference transistors connected in parallel to each other and a output driver circuit having a corresponding plurality of driver transistors connected in parallel with each other. The reference transistors and the driver transistors both have varying widths with the widths of the reference transistors being a binary fraction, for instance one fourth, smaller than the widths of the corresponding output driver transistors. The transistors in the reference circuit are selectively conducted in order to match an impedance of the reference transistors to the impedance of a user selected resistor, representing a fraction of the impedance of a transmission line. The selection of the reference transistors also determines the selection of the driver transistors and consequently causes the impedance of the output driver to match the impedance of the transmission line. The reduction of the reference circuit by the binary fraction reduces the size of the overall circuit, lowers power consumption, and allows a matched layout between the transistors of the output driver and the reference circuit.
Inventors
- 👤 Lee-Lean Shu
- 👤 Kurt Knorpp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0005
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
185 words
A variable impedance output buffer, comprising: a reference circuit comprising a plurality of reference transistors of varying widths connected in parallel to each other; an output driver circuit comprising a plurality of driver transistors of varying widths connected in parallel to each other across a transmission line, said plurality of driver transistors correspond in number to said plurality of reference transistors with a width of each reference transistor being a fraction of a width of a corresponding driver transistor; control means for generating a first control signal to selectively conduct said reference transistors so that an impedance across said reference circuit transistors is matched to an external resistor, said external resistor selected to be equal to said fraction of an impedance of said transmission line; and logic circuitry for receiving said control signal and for generating a second control signal to conduct the driver transistors that correspond to the selected reference circuit transistors; wherein by matching said impedance of said reference transistors to said impedance of said external resistor, an impedance of said output driver circuit is matched to said impedance of said transmission line.
Claim 2
Dependent Claim
185 words
A variable impedance output buffer, comprising: a reference circuit comprising a plurality of reference transistors of varying widths connected in parallel to each other; an output driver circuit comprising a plurality of driver transistors of varying widths connected in parallel to each other across a transmission line, said plurality of driver transistors correspond in number to said plurality of reference transistors with a width of each reference transistor being a fraction of a width of a corresponding driver transistor; control means for generating a first control signal to selectively conduct said reference transistors so that an impedance across said reference circuit transistors is matched to an external resistor, said external resistor selected to be equal to said fraction of an impedance of said transmission line; and logic circuitry for receiving said control signal and for generating a second control signal to conduct the driver transistors that correspond to the selected reference circuit transistors; wherein by matching said impedance of said reference transistors to said impedance of said external resistor, an impedance of said output driver circuit is matched to said impedance of said transmission line.
Claim 3
Dependent Claim
26 words
The variable impedance output buffer according to claim 1, wherein the width of each reference transistor is one-fourth the width of a corresponding output driver transistor.
Claim 4
Dependent Claim
28 words
The variable impedance output buffer according to claim 1, wherein the width of each reference transistor is a binary multiple of a width of an adjacent reference transistor.
Claim 5
Dependent Claim
28 words
The variable impedance output buffer according to claim 1, wherein the width of each driver transistor is a binary multiple of a width of an adjacent driver transistor.
Claim 6
Dependent Claim
27 words
The variable impedance output buffer according to claim 1, wherein the impedance of said external resistor is user selected to match the impedance of said transmission line.
Claim 7
Dependent Claim
62 words
The variable impedance output buffer according to claim 1, wherein said logic circuitry comprises a plurality of NOR gates each receiving a bit of said first control signal in a first input, a data signal in a second input, and generating said second control signal as outputs, said second control signal and said first control signal both having a plurality of bits.
Claim 8
Dependent Claim
56 words
The variable impedance output buffer according to claim 1, wherein said plurality of reference transistors are connected to one end of said external resistor and said control means samples a voltage at said one end of said external resistor in order to match said impedance of said reference transistors to said impedance of said external resistor.
Claim 9
Dependent Claim
42 words
The variable impedance output buffer according to claim 1, wherein said output buffer is fabricated on a single substrate with a layout of the reference transistors in the reference circuit matching a layout of the driver transistors in the output driver circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |