Output circuit having reduced switching noise

Claim 2

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a power supply terminal supplying a voltage of said first logical level; resistor means having one end being connected to said output terminal; and an output driving circuit being connected between said power supply terminal and the other end of said resistor means for receiving said input signal as a control signal and providing said output signal to said output terminal in response to said input signal, said output driving circuit having such current drivability that the rate of change with respect to conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said conversion.

Claim 3

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected to said output terminal; and an output driving circuit being connected between said power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal to said output terminal in response to said input signal, said output driving circuit having such current drivability that the rate of change with respect to conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said conversion, wherein said voltage drop means includes resistor means having a variable resistance value.

Claim 4

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected to said output terminal; and an output driving circuit being connected between said power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal to said output terminal in response to said input signal, said output driving circuit having such current drivability that the rate of change with respect to conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said conversion, wherein said voltage drop means includes resistor means having a variable resistance value.

Claim 5

An output circuit in accordance with claim 2, wherein said resistor means is formed by an element comprising as a plurality of resistors being formed on a substrate, so that said resistance value of said resistor means can be varied by changing the connection pattern of said element.

Claim 6

An output circuit in accordance with claim 3, wherein said element includes a diffused resistor.

Claim 7

An output circuit in accordance with claim 3, wherein said element includes a polysilicon resistor.

Claim 8

An output circuit in accordance with claim 3, wherein said element includes a transistor,

Claim 9

An output circuit in accordance with claim 2, wherein said resistor means comprises: control means, a plurality of elements being connected in a plurality of current paths connecting said output terminal with said output driving circuit for serving as resistors, and at least one switch being independently connected in series to prescribed said elements so that its connection or non-connection state can be controlled by said control means.

Claim 10

An output circuit in accordance with claim 7, wherein prescribed said elements are all said elements.

Claim 11

An output circuit in accordance with claim 7, wherein said elements include diffused resistors.

Claim 12

An output circuit in accordance with claim 7, wherein said elements are polysilicon resistors.

Claim 13

An output circuit in accordance with claim 7, wherein said elements include transistors.

Claim 14

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected to said output terminal; and an output driving circuit being connected between said power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal to said output terminal in response to said input signal, said output driving circuit having such current drivability that the rate of change with respect to conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said conversion, wherein said output driving circuit comprises: a first circuit being connected between said other end of said voltage drop means and said power supply terminal and controlled by said input signal so that its current drivability is monotonically reduced as the level of said output signal outputted from said output terminal is converted from said second logical level to said first logical level and said current drivability is zeroed when the level of said output signal reaches said first logical level, and a second circuit being connected in parallel with said first circuit and controlled by said input signal so that its current drivability is monotonically reduced at a larger reduction rate than said first circuit as the level of said output signal is converted from said second logical level to said first logical level and said current drivability is zeroed before the level of said output signal reaches said first logical level.

Claim 15

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected to said output terminal; and an output driving circuit being connected between said power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal to said output terminal in response to said input signal, said output driving circuit having such current drivability that the rate of change with respect to conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said conversion, wherein said output driving circuit comprises: a first circuit being connected between said other end of said voltage drop means and said power supply terminal and controlled by said input signal so that its current drivability is monotonically reduced as the level of said output signal outputted from said output terminal is converted from said second logical level to said first logical level and said current drivability is zeroed when the level of said output signal reaches said first logical level, and a second circuit being connected in parallel with said first circuit and controlled by said input signal so that its current drivability is monotonically reduced at a larger reduction rate than said first circuit as the level of said output signal is converted from said second logical level to said first logical level and said current drivability is zeroed before the level of said output signal reaches said first logical level.

Claim 16

An output circuit in accordance with claim 12, wherein said second circuit comprises first and second transistors being connected in series in a current path between said other end of said voltage drop means and said power supply terminal, said first transistor has a control electrode being connected to said input terminal, and said second transistor has a control electrode being connected to said current path.

Claim 17

An output circuit in accordance with claim 12, wherein said first circuit comprises a transistor having a control electrode being connected with said input terminal, a first current electrode being connected with said power supply terminal, and a second current electrode being connected with said other end of said voltage drop means respectively.

Claim 18

An output circuit in accordance with claim 12, wherein said first circuit comprises: an inverter having an input end being connected with said input terminal, and a transmission gate being connected between said other end of said voltage drop means and said power supply terminal, and said transmission gate is formed by: a first transistor having a control electrode being connected with said input terminal, a first current electrode being connected with said other end of said voltage drop means, and a second current electrode being connected with said power supply terminal respectively, and a second transistor, being complementary in polarity to said first transistor, having a control electrode being connected with an output end of said inverter, a first current electrode being connected with said other end of said voltage drop means, and a second current electrode being connected with said power supply terminal respectively.

Claim 19

An output circuit in accordance with claim 15, wherein the sum of ON resistance of said transmission gate and the resistance value of said voltage drop means is set to be at least 1/2 and not more than twice the characteristic impedance of a load being connected with said output terminal.

Claim 20

An output circuit in accordance with claim 12, wherein said first circuit comprises a first conductivity type first insulated gate transistor having a source electrode being connected with said power supply terminal, a gate electrode being connected with said input terminal, and a drain electrode being connected with said other end of said voltage drop means, said second circuit comprises: an inverter having an input end being connected to said input terminal, and a second conductivity type second insulated gate transistor having a source electrode being connected with said other end of said voltage drop means, a gate electrode being connected with an output end of said inverter, and a drain electrode being connected with said power supply terminal, and a value obtained by dividing the channel width of said first insulated gate transistor by its channel width is at least twice a value obtained by dividing the channel width of said second insulated gate transistor by its channel width.

Claim 21

An output circuit in accordance with claim 13, wherein said first transistor has one electrode being connected with said other end of said voltage drop means and another electrode being connected with one electrode of said second transistor, while said second transistor has a control electrode being connected with its one electrode and another electrode being connected with said power supply terminal.

Claim 22

An output circuit in accordance with claim 18, wherein both of said first and second transistors include first conductivity type insulated gate transistors.

Claim 23

An output circuit in accordance with claim 13, wherein said first transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said second transistor, while said second transistor has a control electrode being connected with its one electrode and another electrode being connected with said other end of said voltage drop means.

Claim 24

An output circuit in accordance with claim 20, wherein both of said first and second transistors include first conductivity type insulated gate transistors.

Claim 25

An output circuit in accordance with claim 13, wherein said first transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said second transistor, while said second transistor has a control electrode being connected with said power supply terminal and another electrode being connected with said other end of said voltage drop means.

Claim 26

An output circuit in accordance with claim 22, wherein said first transistor is a first conductivity type insulated gate transistor, and said second transistor is a second conductivity type insulated gate transistor.

Claim 27

An output circuit in accordance with claim 13, wherein said first transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said second transistor while said second transistor has another electrode being connected with said output terminal through said voltage drop means and a control electrode being connected with its another electrode or said output terminal.

Claim 28

An output circuit in accordance with claim 24, wherein both of said first and second transistors include first conductivity type insulated gate transistors.

Claim 29

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a first power supply terminal supplying a voltage of said first logical level; resistor means having one end being connected with said output terminal; a second power supply terminal supplying a voltage of said second logical level; a first output driving circuit being connected between said first power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said first logical level to said output terminal in response to said input signal; and a second output driving circuit being connected between said second power supply terminal and said other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said second logical level to said output terminal in response to said input signal, wherein said first output driving circuit has such current drivability that the rate of change with respect to unidirectional conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said unidirectional conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said unidirectional conversion, and said second output driving circuit has such current drivability that the rate of change with respect to backward conversion of the level of said output signal outputted from said output terminal from said first logical level to said second logical level occurring when the level of said output signal is in the vicinity of said first logical level is larger than the rate of change with respect to said backward conversion occurring when the level of said output signal is in the vicinity of said second logical level, said current drivability being monotonically reduced with respect to said backward conversion.

Claim 30

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a first power supply terminal supplying a voltage of said first logical level; resistor means having one end being connected with said output terminal; a second power supply terminal supplying a voltage of said second logical level; a first output driving circuit being connected between said first power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said first logical level to said output terminal in response to said input signal; and a second output driving circuit being connected between said second power supply terminal and said other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said second logical level to said output terminal in response to said input signal, wherein said first output driving circuit has such current drivability that the rate of change with respect to unidirectional conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said unidirectional conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said unidirectional conversion, and said second output driving circuit has such current drivability that the rate of change with respect to backward conversion of the level of said output signal outputted from said output terminal from said first logical level to said second logical level occurring when the level of said output signal is in the vicinity of said first logical level is larger than the rate of change with respect to said backward conversion occurring when the level of said output signal is in the vicinity of said second logical level, said current drivability being monotonically reduced with respect to said backward conversion.

Claim 31

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a first power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected with said output terminal; a second power supply terminal supplying a voltage of said second logical level; a first output driving circuit being connected between said first power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said first logical level to said output terminal in response to said input signal; and a second output driving circuit being connected between said second power supply terminal and said other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said second logical level to said output terminal in response to said input signal, wherein said first output driving circuit has such current drivability that the rate of change with respect to unidirectional conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said unidirectional conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said unidirectional conversion, and said second output driving circuit has such current drivability that the rate of change with respect to backward conversion of the level of said output signal outputted from said output terminal from said first logical level to said second logical level occurring when the level of said output signal is in the vicinity of said first logical level is larger than the rate of change with respect to said backward conversion occurring when the level of said output signal is in the vicinity of said second logical level, said current drivability being monotonically reduced with respect to said backward conversion, wherein said voltage drop means includes resistor means having a variable resistance value.

Claim 32

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a first power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected with said output terminal; a second power supply terminal supplying a voltage of said second logical level; a first output driving circuit being connected between said first power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said first logical level to said output terminal in response to said input signal; and a second output driving circuit being connected between said second power supply terminal and said other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said second logical level to said output terminal in response to said input signal, wherein said first output driving circuit has such current drivability that the rate of change with respect to unidirectional conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second logical level is larger than the rate of change with respect to said unidirectional conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said unidirectional conversion, and said second output driving circuit has such current drivability that the rate of change with respect to backward conversion of the level of said output signal outputted from said output terminal from said first logical level to said second logical level occurring when the level of said output signal is in the vicinity of said first logical level is larger than the rate of change with respect to said backward conversion occurring when the level of said output signal is in the vicinity of said second logical level, said current drivability being monotonically reduced with respect to said backward conversion, wherein said voltage drop means includes resistor means having a variable resistance value.

Claim 33

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a first power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected with said output terminal; a second power supply terminal supplying a voltage of said second logical level; a first output driving circuit being connected between said first power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said first logical level to said output terminal in response to said input signal; and a second output driving circuit being connected between said second power supply terminal and said other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said second logical level to said output terminal in response to said input signal, wherein said first output driving circuit has such current drivability that the rate of change with respect to unidirectional conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second level is larger than the rate of change with respect to said unidirectional conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said unidirectional conversion, and said second output driving circuit has such current drivability that the rate of change with respect to backward conversion of the level of said output signal outputted from said output terminal from said first logical level to said second logical level occurring when the level of said output signal is in the vicinity of said first logical level is larger than the rate of change with respect to said backward conversion occurring when the level of said output signal is in the vicinity of said second logical level, said current drivability being monotonically reduced with respect to said backward conversion, wherein said first output driving circuit comprises: a first circuit being connected between said other end of said voltage drop means and said power supply terminal and controlled by said input terminal so that its current drivability is monotonically reduced along said unidirectional conversion of the level of said output signal being outputted from said output terminal and said current drivability is zeroed when the level of said output signal reaches said first logical level, and a second circuit being connected in parallel with said first circuit and controlled by said input signal so that its current drivability is monotonically reduced at a larger reduction rate than said first circuit along said unidirectional conversion of the level of said output signal and said current drivability is zeroed before the level of said output signal reaches said first logical level, and said second output driving circuit comprises: a third circuit being connected between said other end of said voltage drop means and said second power supply terminal and controlled by said input signal so that its current drivability is monotonically reduced along said backward conversion of the level of said output signal being outputted from said output terminal and said current drivability is zeroed when the level of said output signal reaches said second logical level, and a fourth circuit being connected in parallel with said third circuit and controlled by said input signal so that its current drivability is monotonically reduced at a larger reduction rate than said third circuit along said backward conversion of the level of said output signal and said current drivability is zeroed before the level of said output signal reaches said second logical level.

Claim 34

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a first power supply terminal supplying a voltage of said first logical level; voltage drop means having one end being connected with said output terminal; a second power supply terminal supplying a voltage of said second logical level; a first output driving circuit being connected between said first power supply terminal and the other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said first logical level to said output terminal in response to said input signal; and a second output driving circuit being connected between said second power supply terminal and said other end of said voltage drop means for receiving said input signal as a control signal and providing said output signal of said second logical level to said output terminal in response to said input signal, wherein said first output driving circuit has such current drivability that the rate of change with respect to unidirectional conversion of the level of said output signal outputted from said output terminal from said second logical level to said first logical level occurring when the level of said output signal is in the vicinity of said second level is larger than the rate of change with respect to said unidirectional conversion occurring when the level of said output signal is in the vicinity of said first logical level, said current drivability being monotonically reduced with respect to said unidirectional conversion, and said second output driving circuit has such current drivability that the rate of change with respect to backward conversion of the level of said output signal outputted from said output terminal from said first logical level to said second logical level occurring when the level of said output signal is in the vicinity of said first logical level is larger than the rate of change with respect to said backward conversion occurring when the level of said output signal is in the vicinity of said second logical level, said current drivability being monotonically reduced with respect to said backward conversion, wherein said first output driving circuit comprises: a first circuit being connected between said other end of said voltage drop means and said power supply terminal and controlled by said input terminal so that its current drivability is monotonically reduced along said unidirectional conversion of the level of said output signal being outputted from said output terminal and said current drivability is zeroed when the level of said output signal reaches said first logical level, and a second circuit being connected in parallel with said first circuit and controlled by said input signal so that its current drivability is monotonically reduced at a larger reduction rate than said first circuit along said unidirectional conversion of the level of said output signal and said current drivability is zeroed before the level of said output signal reaches said first logical level, and said second output driving circuit comprises: a third circuit being connected between said other end of said voltage drop means and said second power supply terminal and controlled by said input signal so that its current drivability is monotonically reduced along said backward conversion of the level of said output signal being outputted from said output terminal and said current drivability is zeroed when the level of said output signal reaches said second logical level, and a fourth circuit being connected in parallel with said third circuit and controlled by said input signal so that its current drivability is monotonically reduced at a larger reduction rate than said third circuit along said backward conversion of the level of said output signal and said current drivability is zeroed before the level of said output signal reaches said second logical level.

Claim 35

An output circuit in accordance with claim 28, wherein said second circuit comprises: a first transistor being connected in series in a first current path between said other end of said voltage drop means and said power supply terminal and having a control electrode being connected with said input terminal, and a second transistor being connected in series in said first current path between said voltage drop means and said power supply terminal and having a control electrode being connected with said first current path, and said fourth circuit comprises: a third transistor being connected in series in a second current path between said other end of said voltage drop means and said second power supply terminal and having a control electrode being connected with said input terminal and a fourth transistor being interposed in series in a second current path between said voltage drop means and said second power supply terminal and having a control electrode being connected with said second current path.

Claim 36

An output circuit in accordance with claim 28, wherein said first circuit comprises a first transistor having a control electrode being connected with said input terminal, a first current electrode being connected with said first power supply terminal, and a second current electrode being connected with said other end of said voltage drop means respectively, and said third circuit comprises a second transistor having a control electrode being connected with said input terminal, a first current electrode being connected with said second power supply terminal, and a second current electrode being connected with said output terminal respectively.

Claim 37

An output circuit in accordance with claim 28, wherein said first circuit comprises: a first inverter having an input end being connected with said input terminal, and a first transmission gate being connected between said other end of said voltage drop means and said first power supply terminal, said first transmission gate is formed by a first transistor having a control electrode being connected with said input terminal, a first current electrode being connected with said other end of said voltage drop means, and a second current electrode being connected with said power supply terminal, and a second transistor, being complementary in polarity to said first transistor, having a control electrode being connected with an output end of said first inverter, a first current electrode being connected with said other end of said voltage drop means, and a second current electrode being connected with said power supply terminal respectively, said third circuit comprises: a second inverter having an input end being connected with said input terminal, and a second transmission gate being connected between said other end of said voltage drop means and said second power supply terminal, and said second transmission gate is formed by a third transistor having a control electrode being connected with said input terminal, a first current electrode being connected with said other end of said voltage drop means, and a second current electrode being connected with said second power supply terminal, and a fourth transistor, being complementary in polarity to said third transistor, having a control electrode being connected with an output end of said second inverter, a first current electrode being connected with said other end of said voltage drop means, and a second current electrode being connected with said second power supply terminal respectively.

Claim 38

An output circuit in accordance with claim 31, wherein the sum of ON resistance of said first or second transmission gate and the resistance value of said voltage drop means is set to be at least 1/2 and not more than twice the characteristic impedance of a load which is connected with said one end of said voltage drop means.

Claim 39

An output circuit in accordance with claim 28, further comprising an inverter having an input end being connected with said input terminal, wherein said first circuit comprises a first conductivity type first insulated gate transistor having a source electrode being connected with said first power supply terminal, a gate electrode being connected with said input terminal, and a drain electrode being connected with said other end of said voltage drop means, said second circuit comprises a second conductivity type second insulated gate transistor having a source electrode being connected with said other end of said voltage drop means, a gate electrode being connected with an output end of said inverter, and a drain electrode being connected with said first power supply terminal, said third circuit comprises a second conductivity type third insulated gate transistor having a source electrode being connected with said second power supply terminal, a gate electrode being connected with said input terminal, and a drain electrode being connected with said other end of said voltage drop means, said fourth circuit comprises a first conductivity type fourth insulated gate transistor having a source electrode being connected with said other end of said voltage drop means, a gate electrode being connected with said output end of said inverter, and a drain electrode being connected with said second power supply terminal, a value obtained by dividing the channel width of said first insulated gate transistor by its channel width of said first insulated gate transistor by its channel width is at least twice a value obtained by dividing the channel width of said second insulated gate transistor by its channel length, and a value obtained by dividing the channel width of said third insulated gate transistor by its channel length is at least twice a value obtained by dividing the channel width of said fourth insulated gate transistor by its channel length.

Claim 40

An output circuit in accordance with claim 29, wherein said first transistor has one electrode being connected with said other end of said voltage drop means and another end being connected to one electrode of said second transistor, while said second transistor has a control electrode being connected with its one or other electrode and another electrode being connected with said first power supply terminal, and said third transistor has one electrode being connected to said other end of said voltage drop means and another electrode being connected to one electrode of said fourth transistor, while said fourth transistor has a control electrode being connected with its one or other electrode and another electrode being connected with said second power supply terminal.

Claim 41

An output circuit in accordance with claim 34, wherein both of said first and second transistors are first conductivity type insulated gate transistors, and both of said third and fourth transistors are second conductivity type insulated gate transistors.

Claim 42

An output circuit in accordance with claim 29, wherein said first transistor has one electrode being connected with said first power supply terminal and another electrode being connected with one electrode of said second transistor while said second transistor has a control electrode being connected with its one or other electrode and another electrode being connected with said other end of said voltage drop means, and said third transistor has one electrode being connected with said second power supply terminal and another electrode being connected with one electrode of said fourth transistor while said fourth transistor has a control electrode being connected with its one or other electrode and another electrode being connected with one end of said voltage drop means.

Claim 43

An output circuit in accordance with claim 36, wherein both of said first and second transistors are first conductivity type insulated gate transistors, and both of said third and fourth transistors are second conductivity type insulated gate transistors.

Claim 44

An output circuit in accordance with claim 29, wherein said first transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said second transistor while said second transistor has a control electrode being connected with said power supply terminal and another electrode being connected to said other end of said voltage drop means, and said third transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said fourth transistor while said fourth transistor has a control electrode being connected with said other end of said voltage drop means and another electrode being connected with said other end of said voltage drop means.

Claim 45

An output circuit in accordance with claim 38, wherein said first transistor is a first conductivity type insulated gate transistor, said second transistor is a second conductivity type insulated gate transistor, and both of said third and fourth transistors are first conductivity type insulated gate transistors.

Claim 46

An output circuit in accordance with claim 29, wherein said first transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said second transistor while said second transistor has another electrode being connected with said output terminal through said voltage drop means and a control electrode being connected with its another electrode or said output terminal, and said third transistor has one electrode being connected with said power supply terminal and another electrode being connected with one electrode of said fourth transistor while said fourth transistor has another electrode being connected with said output terminal through said voltage drop means and a control electrode being connected with its another electrode or said output terminal.

Claim 47

An output circuit in accordance with claim 40, wherein both of said first and second transistors are first conductivity type insulated gate transistors, and both of said third and fourth transistors are second conductivity type insulated gate transistors.

Claim 48

An output circuit in accordance with claim 28, wherein said first circuit comprises a first conductivity type first insulated gate transistor having a source electrode being connected with said first power supply terminal, a gate electrode being connected with said input terminal, and a drain electrode being connected with one end of said voltage drop means, said second circuit comprises: an inverter having an input end being connected with said input terminal, and a second conductivity type second insulated gate transistor having a source electrode being connected with said other end of said voltage drop means, a gate electrode being connected with an output end of said inverter, and a drain electrode being connected with said first power supply terminal, and said fourth circuit comprises: a first transistor being connected in series in a current path between said other end of said voltage drop means and said second power terminal and having a control electrode being connected with said input terminal, and a second transistor being connected in series in said current path between said other end of said voltage drop means and said second power supply terminal and having a control electrode being connected with said current path.

Claim 49

An output circuit in accordance with claim 2, wherein said the output driving circuit comprising: first switching means being connected between said other end of said voltage drop means and said power supply terminal and controlled by said input signal for switching, second switching means being supplied with an output signal from said output terminal through said first switching means and said voltage drop means for switching off when the level of said output signal exceeds a prescribed value, and another voltage drop means being connected in parallel with said second switching means.