US5148048A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS output circuit having controlled slope
Assignee: Toshiba Corp
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Filing: 1991-06-03
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Granted: 1992-09-15
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Expires: 2011-06-03
Abstract
Abstract Two p-channel MOS transistors are inserted in series between the positive power supply and the output terminal, whereas two n-channel MOS transistors are inserted in series between the output terminal and the negative power supply. Across the source and drain of one of the p-channel MOS transistors, a first diode is connected in parallel in the forward direction. Similarly, across the source and drain of one of the n-channel MOS transistors, a second diode is connected in parallel in the forward direction.
Inventors
- 👤 Masayuki Kawasaki
- 👤 Kiyomitsu Takatani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:04
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
220 words
A CMOS output circuit comprising: a first power supply of high potential; a second power supply of low potential; a signal output terminal; a first MOS transistor of a P-channel type having a source, a drain and a gate, said source being connected to said first power supply; a second MOS transistor of a P-channel type having a source, a drain and a gate, said source connected to the drain of said first MOS transistor, said drain being connected to said signal output terminal; a third MOS transistor of an N-channel type having a source, a drain and a gate, said source being connected to said second power supply; a fourth MOS transistor of an N-channel type having a source, a drain and a gate, said source connected to the drain of said third MOS transistor, said drain connected to said signal output terminal wherein each said gate of said first, second, third and fourth MOS transistor receives a first or a second input signal; a first diode having an anode connected to the source of said first MOS transistor, and a cathode connected to the drain of said first MOS transistor; and a second diode having an anode connected to the drain of said third MOS transistor, and a cathode connected to the source of said third MOS transistor.
Claim 2
Dependent Claim
220 words
A CMOS output circuit comprising: a first power supply of high potential; a second power supply of low potential; a signal output terminal; a first MOS transistor of a P-channel type having a source, a drain and a gate, said source being connected to said first power supply; a second MOS transistor of a P-channel type having a source, a drain and a gate, said source connected to the drain of said first MOS transistor, said drain being connected to said signal output terminal; a third MOS transistor of an N-channel type having a source, a drain and a gate, said source being connected to said second power supply; a fourth MOS transistor of an N-channel type having a source, a drain and a gate, said source connected to the drain of said third MOS transistor, said drain connected to said signal output terminal wherein each said gate of said first, second, third and fourth MOS transistor receives a first or a second input signal; a first diode having an anode connected to the source of said first MOS transistor, and a cathode connected to the drain of said first MOS transistor; and a second diode having an anode connected to the drain of said third MOS transistor, and a cathode connected to the source of said third MOS transistor.
Claim 3
Dependent Claim
29 words
A CMOS output circuit according to claim 1, wherein the gate of said second MOS transistor and the gate of said fourth MOS transistor are connected to each other.
Claim 4
Dependent Claim
48 words
A CMOS output circuit according to claim 1, wherein: the gate of said first MOS transistor and the gate of said second MOS transistor are connected to each other, the gate of said third MOS transistor and the gate of fourth MOS transistor are connected to each other.
Claim 5
Dependent Claim
43 words
A CMOS output circuit according to claim 1, wherein: the conductance of said first MOS transistor is set smaller than that of said second MOS Transistor, the conductance of said third MOS transistor is set smaller than that of said fourth MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |