US4626715A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS FET amplifier output stage
Assignee: Pioneer Corp
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Filing: 1984-02-28
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Granted: 1986-12-02
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Expires: 2004-02-28
Abstract
Abstract An output circuit particularly adapted for use in a pulse width modulation amplifier having a significantly reduced power loss during switching times. Inductors are coupled in series with the signal channels of two push-pull connected switching elements. High-speed diodes are coupled in parallel with the series combinations of switching elements and inductors.
Inventors
- 👤 Satoshi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:29
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/02; H03K17/00; H03K17/04; H03K17/041; H03K17/0416; H03K17/04163; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K17/667; H03K17/687; H03K17/6871; H03K17/6872; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
224 words
An output circuit comprising: first and second switching elements, said first switching element having a first signal channel terminal coupled to a positive power source terminal and a second signal channel terminal coupled to an intermediate terminal, said second switching element having a first signal channel terminal coupled to a negative power source terminal and a second signal channel terminal coupled to said intermediate terminal, and said first and second switching elements having respective control terminals receiving control signals, said intermediate terminal providing an output signal; a first inductor coupled in series with the signal channel of said first switching element between said positive power source terminal and said intermediate terminal; a second inductor coupled in series with the signal channel of said second switching element between said intermediate terminal and said negative power source terminal; a first diode connected in parallel with the series coupling of said first transistor and said first inductor and having its anode coupled to said intermediate terminal and its cathode coupled to said positive power source terminal; and a second diode connected in parallel with the series coupling of said second transistor and said second inductor and having its cathode coupled to said intermediate terminal and its anode coupled to said negative power source terminal; whereby power loss occurring at switching times of said control signals is reduced.
Claim 2
Dependent Claim
224 words
An output circuit comprising: first and second switching elements, said first switching element having a first signal channel terminal coupled to a positive power source terminal and a second signal channel terminal coupled to an intermediate terminal, said second switching element having a first signal channel terminal coupled to a negative power source terminal and a second signal channel terminal coupled to said intermediate terminal, and said first and second switching elements having respective control terminals receiving control signals, said intermediate terminal providing an output signal; a first inductor coupled in series with the signal channel of said first switching element between said positive power source terminal and said intermediate terminal; a second inductor coupled in series with the signal channel of said second switching element between said intermediate terminal and said negative power source terminal; a first diode connected in parallel with the series coupling of said first transistor and said first inductor and having its anode coupled to said intermediate terminal and its cathode coupled to said positive power source terminal; and a second diode connected in parallel with the series coupling of said second transistor and said second inductor and having its cathode coupled to said intermediate terminal and its anode coupled to said negative power source terminal; whereby power loss occurring at switching times of said control signals is reduced.
Claim 3
Dependent Claim
14 words
The output circuit of claim 1, therein said switching elements comprise power MOS FETs.
Claim 4
Dependent Claim
14 words
The output circuit of claim 1, where said switching elements comprise bidirectional switching elements.
Claim 5
Dependent Claim
17 words
The output circuit of claim 1, wherein inductances of said inductors are no greater than 2 microhenries.
Claim 6
Dependent Claim
42 words
The output circuit of claim 1, further comprising low pass filter means connected to said intermediate terminal for filtering said output signal and providing a filtered output signal, whereby said output circuit suppresses a reverse current of said low pass filter means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |