Abstract A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.
In a D-type flip-flop that transfers input data to first and second outputs, the second output being the complement of the first output, via a master latch and a slave latch connected in series, on transitions of a clock signal, override circuitry for loading override data into the flip-flop in response to a load signal which is asynchronous to the clock signal to replace the input data, the override circuitry comprising: (a) a master latch comprising (i) a master storage buffer for storing the input data; (ii) a transmission gate for transferring the input data to the master storage buffer on a first phase of the clock signal; (iii) means for inverting the input data stored in the master storage buffer; (iv) feedback means for transferring the inverted input data to an input of the master storage buffer on a second phase of the clock signal; (v) means for replacing the input data stored in the master latch with the override data in response to the load signal; and (b) a slave latch comprising (i) a slave storage buffer for storing input data received from the master latch; (ii) a second transmission gate responsive to the second phase of the clock signal for transferring input data from the master latch to the slave storage buffer; (iii) means for inverting the input data stored in the slave storage buffer; (iv) feedback means for transferring the inverted input data to an input of the slave storage buffer on the first phase of the clock signal; (v) means for replacing the input data stored in the slave latch with override data in response to the load signal.
Claim 2
Dependent Claim
274 words
In a D-type flip-flop that transfers input data to first and second outputs, the second output being the complement of the first output, via a master latch and a slave latch connected in series, on transitions of a clock signal, override circuitry for loading override data into the flip-flop in response to a load signal which is asynchronous to the clock signal to replace the input data, the override circuitry comprising: (a) a master latch comprising (i) a master storage buffer for storing the input data; (ii) a transmission gate for transferring the input data to the master storage buffer on a first phase of the clock signal; (iii) means for inverting the input data stored in the master storage buffer; (iv) feedback means for transferring the inverted input data to an input of the master storage buffer on a second phase of the clock signal; (v) means for replacing the input data stored in the master latch with the override data in response to the load signal; and (b) a slave latch comprising (i) a slave storage buffer for storing input data received from the master latch; (ii) a second transmission gate responsive to the second phase of the clock signal for transferring input data from the master latch to the slave storage buffer; (iii) means for inverting the input data stored in the slave storage buffer; (iv) feedback means for transferring the inverted input data to an input of the slave storage buffer on the first phase of the clock signal; (v) means for replacing the input data stored in the slave latch with override data in response to the load signal.