US4394586A
Expired / Lapsed
US
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Dynamic divider circuit
Assignee: SUWA A Co OF JAPAN KK
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Filing: 1973-10-19
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Granted: 1983-07-19
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Expires: 1993-10-19
Abstract
Abstract A dynamic divider circuit comprised of insulating gate field effect transistors and capable of operation using minimal current consumption in a reduced space is provided. Master and slave multiple inverters and an intermediate inverter are formed from complementary connected P-channel and N-channel insulated gate field effect transistors, the master and the slave inverter being directly coupled to the master inverter. The coupling of the master, intermediate, and slave inverters providing reduced current consumption and a more simplified circuit by utilizing the parasitic capacitance of said field effect transistors as a memory.
Inventors
- 👤 Shinji Morozumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:05
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K23/00; H03K23/40; H03K23/42
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
266 words
A dynamic binary divider circuit comprised of an intermediate inverter, a first multiple inverter and a second multiple inverter, said intermediate inverter being formed by the complementary connection of a P-channel transistor and an N-channel transistor, each said first and second multiple inverters being formed from the serial connection of two-series-connected P-channel transistors to two series connected N-channel transistors respectively, the drain terminals of one of the P-channel and N-channel transistors of each multiple inverter being connected together to define an output terminal of the respective multiple inverter, the gate terminals of said one of the P-channel and N-channel transistors of each multiple inverter being connected together to define an input terminal of the respective inverter, said output terminal of said first multiple inverter being coupled through said intermediate inverter to the input of said second multiple inverter, the output terminal of said second multiple inverter being coupled to the input terminal of said first multiple inverter, the other P-channel transistor of said first multiple inverter and the other N-channel transistor of said second multiple inverter being connected for receipt at the respective gate terminals thereof with a first clock pulse and the other N-channel transistor of said first multiple inverter and the other P-channel transistor of said second multiple inverter being connected for receipt at the respective gate terminals thereof with a second clock pulse which is the complement of said first clock pulse whereby the parasitic capacitance at respective outputs of said first and second multiple inverters is utilized as a memory means, so that a division of said clock pulse applied is effected.
Claim 2
Dependent Claim
266 words
A dynamic binary divider circuit comprised of an intermediate inverter, a first multiple inverter and a second multiple inverter, said intermediate inverter being formed by the complementary connection of a P-channel transistor and an N-channel transistor, each said first and second multiple inverters being formed from the serial connection of two-series-connected P-channel transistors to two series connected N-channel transistors respectively, the drain terminals of one of the P-channel and N-channel transistors of each multiple inverter being connected together to define an output terminal of the respective multiple inverter, the gate terminals of said one of the P-channel and N-channel transistors of each multiple inverter being connected together to define an input terminal of the respective inverter, said output terminal of said first multiple inverter being coupled through said intermediate inverter to the input of said second multiple inverter, the output terminal of said second multiple inverter being coupled to the input terminal of said first multiple inverter, the other P-channel transistor of said first multiple inverter and the other N-channel transistor of said second multiple inverter being connected for receipt at the respective gate terminals thereof with a first clock pulse and the other N-channel transistor of said first multiple inverter and the other P-channel transistor of said second multiple inverter being connected for receipt at the respective gate terminals thereof with a second clock pulse which is the complement of said first clock pulse whereby the parasitic capacitance at respective outputs of said first and second multiple inverters is utilized as a memory means, so that a division of said clock pulse applied is effected.
Claim 3
Dependent Claim
50 words
A divider circuit as recited in claim 1, wherein the respective source terminal of each of the P-channel transistors of the first and second inverters are connected together and wherein the respective source terminal of each of the other N-channel transistors of the first and second inverters are connected together.
Claim 4
Dependent Claim
266 words
A dynamic divider circuit for use in an electronic timepiece comprising a master inverter, a slave inverter, and an intermediate inverter, said master and slave inverters each including first and second serially connected P-channel field effect transistors and first and second N-channel serially connected transistors, the second N-channel and P-channel transistors of each of said master and slave inverters being complementary coupled so as to define master and slave inverter output terminals and a master and slave inverter input terminal, the respective gate terminals of the first N-channel transistor of said master inverter and the first P-channel transistor of said slave inverter are connected to receive a first clock pulse φ having a first frequency, the respective gate terminals of the first P-channel of said master inverter and the first N-channel transistor of said slave inverter connected to receive a second clock pulse φ which is the complement of said first clock pulse, the output of said master inverter producing a signal M having a second frequency equal to one-half said first frequency, said master inverter being coupled through said intermediate inverter to produce a complementary input M for application to said slave inverter, and the output of slave inverter being a frequency equal to said second frequency but delayed by a period equal to one-half the period of first clock pulse φ, applied to the input of said master inverter, whereby the parasitic capacitance at the common output terminals of said master and slave inverters is utilized as a memory means, the leakage current and the effective capacitance determining the operating frequencies of said divider.
Claim 5
Dependent Claim
266 words
A dynamic divider circuit for use in an electronic timepiece comprising a master inverter, a slave inverter, and an intermediate inverter, said master and slave inverters each including first and second serially connected P-channel field effect transistors and first and second N-channel serially connected transistors, the second N-channel and P-channel transistors of each of said master and slave inverters being complementary coupled so as to define master and slave inverter output terminals and a master and slave inverter input terminal, the respective gate terminals of the first N-channel transistor of said master inverter and the first P-channel transistor of said slave inverter are connected to receive a first clock pulse φ having a first frequency, the respective gate terminals of the first P-channel of said master inverter and the first N-channel transistor of said slave inverter connected to receive a second clock pulse φ which is the complement of said first clock pulse, the output of said master inverter producing a signal M having a second frequency equal to one-half said first frequency, said master inverter being coupled through said intermediate inverter to produce a complementary input M for application to said slave inverter, and the output of slave inverter being a frequency equal to said second frequency but delayed by a period equal to one-half the period of first clock pulse φ, applied to the input of said master inverter, whereby the parasitic capacitance at the common output terminals of said master and slave inverters is utilized as a memory means, the leakage current and the effective capacitance determining the operating frequencies of said divider.
Claim 6
Dependent Claim
38 words
A divider circuit as recited in claim 3, wherein the respective drain and gate terminals of said second N-channel and P-channel transistors of each of said master and slave inverters are connected together to define said complementary connection.
Claim 7
Dependent Claim
31 words
A divider circuit as recited in claim 4, wherein the respective drain terminal of each first N-channel and P-channel transistor is connected to the respective source of the transistor series-connected therewith.
Claim 8
Dependent Claim
48 words
A divider circuit as recited in claim 5, including a source of voltage and ground, wherein the respective source terminals of said first P-channel transistors are connected together, and the respective drain terminals of said first N-channel transistors are connected together between said source of voltage and ground.
Claim 9
Dependent Claim
28 words
A divider circuit as recited in claim 6, wherein said intermediate inverter includes a P-channel and an N-channel transistor complementary connected between said source of voltage and ground.
Claim 10
Dependent Claim
129 words
The combination comprising, first and second selectively operative inverting means, each inverting means having a signal input terminal, a power input terminal means and an output; an inverter having an input connected to said output of said first inverting means, and having an output connected to said signal input terminal of said second inverting means; means connecting said output of said second inverting means to said signal input terminal of said first inverting means; and means for applying control signals to the power input terminal means of said first and second inverting means to render operative said first inverting means and render inoperative said second inverter during one time interval and for rendering inoperative said first inverting means and rendering operative said second inverting means during another time interval.
Claim 11
Dependent Claim
129 words
The combination comprising, first and second selectively operative inverting means, each inverting means having a signal input terminal, a power input terminal means and an output; an inverter having an input connected to said output of said first inverting means, and having an output connected to said signal input terminal of said second inverting means; means connecting said output of said second inverting means to said signal input terminal of said first inverting means; and means for applying control signals to the power input terminal means of said first and second inverting means to render operative said first inverting means and render inoperative said second inverter during one time interval and for rendering inoperative said first inverting means and rendering operative said second inverting means during another time interval.
Claim 12
Dependent Claim
79 words
The combination comprising, first and second selectively operative inverter means each having an input and an output; a continuously operative inverter having an input coupled to said output of said first inverter means, and having an output coupled to said input of said second inverter means; means coupling said output of said second inverter means to said input of said first inverter means; and means for rendering operative one of said first and second inverter means at a time.
Claim 13
Dependent Claim
79 words
The combination comprising, first and second selectively operative inverter means each having an input and an output; a continuously operative inverter having an input coupled to said output of said first inverter means, and having an output coupled to said input of said second inverter means; means coupling said output of said second inverter means to said input of said first inverter means; and means for rendering operative one of said first and second inverter means at a time.
Claim 14
Dependent Claim
137 words
The combination as claimed in claim 9 wherein each one of said first and second inverter means includes first and second transistors each having a control electrode and a conduction path, wherein the control electrodes of the two transistors of each one of said first and second inverter means are connected to said input of the first and second inverter means, respectively, and wherein the conduction paths of said first and second transistors of said first and second inverter means are coupled to said output of said first and second inverter means, respectively, for charging and discharging the respective said output, when said inverter means is rendered operative; and wherein each one of said first and second inverter means includes means for selectively applying an operating potential across the conduction paths of said first and second transistors.
Claim 15
Dependent Claim
206 words
The combination comprising, two power terminals for the application therebetween of an operating potential; first and second inverting means connected in parallel between said two power terminals; each inverting means having an input and an output and including a first switch means connected in series with a first controllable conduction means between one of said power terminals and said output and including a second switch means connected in series with a second controllable conduction means between the other one of said power terminals and said output; an inverter having an input and an output, the input of said inverter being connected to the output of said first inverting means and the output of said inverter being connected to the input of said second inverting means; means connecting the output of said second inverting means to the input of said first inverting means; and means for applying signals to said switch means for during one time interval closing the two switch means of said first inverting means and opening the two switch means of said second inverting means and for during a second succeeding time interval opening the two switch means of said first inverting means and closing the two switch means of said second inverting means.
Claim 16
Dependent Claim
206 words
The combination comprising, two power terminals for the application therebetween of an operating potential; first and second inverting means connected in parallel between said two power terminals; each inverting means having an input and an output and including a first switch means connected in series with a first controllable conduction means between one of said power terminals and said output and including a second switch means connected in series with a second controllable conduction means between the other one of said power terminals and said output; an inverter having an input and an output, the input of said inverter being connected to the output of said first inverting means and the output of said inverter being connected to the input of said second inverting means; means connecting the output of said second inverting means to the input of said first inverting means; and means for applying signals to said switch means for during one time interval closing the two switch means of said first inverting means and opening the two switch means of said second inverting means and for during a second succeeding time interval opening the two switch means of said first inverting means and closing the two switch means of said second inverting means.
Claim 17
Dependent Claim
134 words
The combination as claimed in claim 11, wherein each one of said first controllable conduction means includes a first transistor having first and second electrodes defining the ends of a conduction path and a control electrode for controlling the conductivity of said path, each said first switch means being connected in series with the conduction path of the associated said first transistor; wherein each one of said second controllable conduction means includes a second transistor having first and second electrodes defining the ends of a conduction path and a control electrode, each said second switch means being connected in series with the conduction path of the associated said second transistor; and wherein the control electrodes of said first and second transistors of each inverting means are connected to the input of that inverting means.
Claim 18
Dependent Claim
50 words
The combination as claimed in claim 12 wherein each one of said switch means is a switching transistor having a conduction path and a control electrode; and wherein said means for applying signals to said switch means includes means for applying signals to the control electrodes of said switching transistors.
Claim 19
Dependent Claim
35 words
The combination as claimed in claim 13 wherein one of the two switching transistors is of one conductivity type and the other one of the two switching transistors is of a second, complementary, conductivity type.
Claim 20
Dependent Claim
69 words
The combination as claimed in claim 13, wherein said first and second transistors of each inverting means are of complementary conductivity type and wherein each switching transistor is of the same conductivity type as the transistor to whose conduction path it is serially connected; and wherein said means for applying signals include means for applying complementary signals to the control electrodes of the switching transistors of an inverting means.
Claim 21
Dependent Claim
76 words
The combination as claimed in claim 15, wherein each one of said transistors is an insulated gate field effect transistor having a gate electrode and source and drain electrodes wherein said source electrode is said first electrode, said drain electrode is said second electrode and wherein said gate electrode is said control electrode; and wherein said inverter includes two transistors of complementary conductivity type having their conduction paths connected in series between said two power terminals.
Claim 22
Dependent Claim
20 words
The combination as claimed in claim 16, wherein said two transistors of said inverter are insulated gate field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-18 | 1987-01-17 | 1987-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-18 | 1991-01-17 | 1991-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-18 | 1995-01-17 | 1995-07-19 | $7700.00 | Window Closed / Lapsed |