Logic circuit using complementary type insulated gate field effect transistors

Claim 2

A logic circuit comprising: input and output terminals, said input terminals supplying binary coded signals; first and second sources of power, said first source being more positive than said second source; a signal storage logic circuit element which includes at least one complementary pair of one N channel and one P channel insulated gate field effect transistors (IGFET) for signal storage, the gate electrodes of said IGFET''s being mutually connected together to the input terminal, the drain electrodes of said IGFET''s being connected together to the output terminal, and the substrate electrodes of said N channel IGFET and said P channel IGFET being directly connected respectively to the second and first power sources; two switching elements respectively connected between the source electrodes of each of said complementary pair of signal storage IGFET''s and said first and second power sources; and means for supplying the gates of said switching elements with clock pulses of a predetermined phase so that when the binary coded signals are supplied at the input terminal, the logic circuit momentarily stores input signals in the gate capacitance present between ground and the commonly connected gates of said complementary pair of signal storage IGFET''s and then, when said clock pulse is impressed on the gates of said switching elements, the stored input data signals are produced from the output terminal as output signals time delayed half a bit and inverted in phase from the input signals.

Claim 3

A logic circuit according to claim 1 wherein said signal storage logic circuit element further includes at least one additional P channel IGFET having its drain-source path connected in parallel to the drain-source path of said P channel IGFET constituting said complementary pair of signal storage IGFET''s and at least one additional N channel IGFET having its drain-source path connected between the source of said N channel IGFET constituting said complementary pai of signal storage IGFET''s and the corresponding one of said switching elements, the gates of said additional P and N channel IGFET''s being connected together to an additional input terminal to be supplied with additional binary coded signals separate from said first-mentioned binary coded signals, the logic circuit operating as a NAND logic circuit with respect to the binary input signals.

Claim 4

A logic circuit according to claim 1 wherein said signal storage logic circuit element further includes at least one additional N channel IGFET having its drainsource path connected in parallel to the drain-source path of said N channel IGFET constituting said complementary pair of signal storage IGFET''s and at least one additional P channel IGFET having its drain-source path connected between the source of said P channel IGFET constituting said complementary pair of signal storage IGFET''s and the corresponding one of said switching elements, the gates of said additional P and N channel IGFET''s being connected together to an additional input terminal to be supplied with additional binary coded signals separate from said first-mentioned binary coded signals, the logic circuit operating as a NOR logic circuit with respect to the binary input signals.

Claim 5

A logic circuit according to claim 1 wherein said switching elements comprise a complementary pair of IGFET''s which include an N channel IGFET having its drain-source path connected between the source of said N channel IGFET constituting said complementary pair of signal storage IGFET''s and said negative power source and having its gate impressed with a clock pulse of a predetermined phase, and a P channel IGFET having its drain-source path connected between the source of said P channel IGFET constituting said complementary pair of signal storage IGFET''s and said positive power source and having its gate impressed with a clock pulse of an inverted phase to that of said clock pulse to be impressed on the gate of said paired N channel IGFET.

Claim 6

A logic circuit according to claim 1 wherein said switching elements comprise two IGFET''s having their drain-source paths connected between the sources of said P and N channel IGFET''s constituting said complementary pair of signal storage IGFET''s and said positive and negative power sources and having their gates impressed with clock pulses of the same phase.

Claim 7

A logic circuit according to claim 5 wherein said switching elements comprise two P channel IGFET''s.

Claim 8

A logic circuit according to claim 5 wherein said switching elements comprise two N channel IGFET''s.

Claim 9

A logic circuit according to claim 1 wherein said switching elements are relays.

Claim 10

A shift register comprising a plurality of caScade connected shift register units, each shift register unit comprising a pair of basic logic circuits, each basic logic circuit including a logic circuit element comprised of at least one complementary type IGFET unit, each unit comprising at least one pair of complementary type insulated gate field effect transistors (IGFET''s), each pair including an N channel IGFET and a P channel IGFET; each basic logic circuit having an input terminal to which there are connected the gate electrode of said complementary IGFET''s and an output terminal to which there are connected to the drain electrodes of said IGFET''s; a negative source of power coupled to the source and connected directly to the substrate electrodes of the complementary N channel IGFET and a positive source of power coupled to the source and connected directly to the substrate electrodes of the complementary P channel IGFET; and switching elements connected between the source electrodes of said complementary IGFET''s and said positive and negative power sources; the output terminal of one of said pair of basic logic circuits being connected to the input terminal of the other, so as to perform a one-bit delay; the input terminal of the switching element constituting a first basic logic circuit being adapted to receive a first clock pulse having a prescribed period, and the input terminal of the switching element constituting said other basic logic circuit being adapted to receive a second clock pulse differentiated in phase from the first clock pulse to thereby carry out the shifting of data in said shift register.

Claim 11

A shift register comprising a plurality of caScade connected shift register units, each shift register unit comprising a pair of basic logic circuits, each basic logic circuit including a logic circuit element comprised of at least one complementary type IGFET unit, each unit comprising at least one pair of complementary type insulated gate field effect transistors (IGFET''s), each pair including an N channel IGFET and a P channel IGFET; each basic logic circuit having an input terminal to which there are connected the gate electrode of said complementary IGFET''s and an output terminal to which there are connected to the drain electrodes of said IGFET''s; a negative source of power coupled to the source and connected directly to the substrate electrodes of the complementary N channel IGFET and a positive source of power coupled to the source and connected directly to the substrate electrodes of the complementary P channel IGFET; and switching elements connected between the source electrodes of said complementary IGFET''s and said positive and negative power sources; the output terminal of one of said pair of basic logic circuits being connected to the input terminal of the other, so as to perform a one-bit delay; the input terminal of the switching element constituting a first basic logic circuit being adapted to receive a first clock pulse having a prescribed period, and the input terminal of the switching element constituting said other basic logic circuit being adapted to receive a second clock pulse differentiated in phase from the first clock pulse to thereby carry out the shifting of data in said shift register.

Claim 12

A logic circuit according to claim 9 wherein the logic circuit element is an inverter.

Claim 13

A logic circuit according to claim 9 wherein the logic circuit element is a NAND logic circuit.

Claim 14

A logic circuit according to claim 9 wherein the logic circuit element is a NOR logic circuit.