Data translating circuit

Claim 2

A data translating stage comprising: two active elements, each having a conduction path and a control electrode for controlling the conductance of said path; two asymmetrically conducting elements; first and second current carrying paths, each path connected between a capacitive output node and a different one of first and second clock terminals, each of said paths including the conduction path of one of said elements in series with one of said asymmetrically conducting elements, one of said asymmetrically conducting elements poled for charging said node and the other poled for discharging said node; means for concurrently applying an input signal to the control electrodes of said two active elements for placing one of their conduction paths in a relatively low impedance condition and the other one in a relatively high impedance condition and means for applying clock signals to said first and second terminals of a sense, during a first time interval, to permit conduction through the one of said first and second paths having an active element which exhibits a relatively low impedance and of a sense, during a following time interval, to prevent the flow of current in either one of said paths.

Claim 3

A data translating stage comprising: two active elements, each having a conduction path and a control electrode for controlling the conductance of said path; two asymmetrically conducting elements; first and second current carrying paths, each path connected between a capacitive output node and a different one of first and second clock terminals, each of said paths including the conduction path of one of said elements in series with one of said asymmetrically conducting elements, one of said asymmetrically conducting elements poled for charging said node and the other poled for discharging said node; means for concurrently applying an input signal to the control electrodes of said two active elements for placing one of their conduction paths in a relatively low impedance condition and the other one in a relatively high impedance condition and means for applying clock signals to said first and second terminals of a sense, during a first time interval, to permit conduction through the one of said first and second paths having an active element which exhibits a relatively low impedance and of a sense, during a following time interval, to prevent the flow of current in either one of said paths.

Claim 4

A data translating stage comprising: two active elements, each having a conduction path and a control electrode for controlling the conductance of said path; two asymmetrically conducting elements; first and second current carrying paths, each path connected between a capacitive output node and a different one of first and second clock terminals, each of said paths including the conduction path of one of said elements in series with one of said asymmetrically conducting elements, one of said asymmetrically conducting elements poled for charging said node and the other poled for discharging said node; means for concurrently applying an input signal to the control electrodes of said two active elements for placing one of their conduction paths in a relatively low impedance condition and the other one in a relatively high impedance condition and means for applying clock signals to said first and second terminals of a sense, during a first time interval, to permit conduction through the one of said first and second paths having an active element which exhibits a relatively low impedance and of a sense, during a following time interval, to prevent the flow of current in either one of said paths.

Claim 5

The combination as claimed in claim 1 wherein each one of said active elements comprises a field-effect transistor; each transistor having source and drain electrodes defining the ends of a conduction channel through which current can flow bidirectionally and each transistor having a gate electrode; wherein said gate electrode is said control electrode and said conduction channel is said conduction path; and wherein each one of said asymmetrically conducting element comprises a diode poled to allow conduction in only one direction through the transistor to which it is connected.

Claim 6

The combination as claimed in claim 2 wherein the anode of the diode of said first path is connected in common with the cathode of the diode of said second path to said output node; wherein the conduction channel of the transistors of said first path is connected between the cathode of the diode of said first path and said first clock terminal; wherein the conduction channel of the transistor of said second path is connected between the anode of the diode of said second path and said second clock terminal; and wherein the clock signal applied at said second terminal is the complement of the clock signal applied at said first terminal.

Claim 7

The combination as claimed in claim 2, wherein the gate electrodes of the transistors of said first and second paths are connected in common; wherein the drain electrodes of the transistors of the two paths are connected in common to said output node; wherein the source electrode of the transistor of said first path is connected to the cathode of the diode of said first path whose anode is connected to said first clock terminal; wherein the source electrode of the transistor of said second path is connected to the anode of the diode of said second path whose cathode is connected to said second terminal; and wherein the clock signal applied to said first terminal is the complement of the signal applied at said second terminal.

Claim 8

The combination as claimed in claim 2 further including a data input terminal and two field-effect transistors of different conductivity type having their conduction channels connected in parallel for forming a transmission gate; means connecting one end of the conduction channels of said transmission gate transistors to said data input terminal, and means connecting the other end of their conduction channels to the gate electrodes of the transistors of said first and second paths; and means for applying a second clock signal to the gate electrodes of said two transmission gate transistors for enabling said transmission gate during a time interval other than said first time interval.

Claim 9

The combination as claimed in claim 3 wherein the transistor in said first path is of one conductivity type and wherein the transistor in said second path is of opposite conductivity type.

Claim 10

The combination comprising: first and second field effect transistors having a conduction path through which current can flow bidirectionally and a control electrode; a first path comprising the conduction path of said first transisTor connected in series with a first diode between a first terminal and a capacitive output node; said first diode being poled to allow conduction in only one direction through said first transistor; a second path comprising the conduction path of said second transistor connected in series with a second diode between a second terminal and said output node; said second diode being poled to allow conduction in only one direction through said second transistor; data input means connected to the control electrode of said two transistors for turning-on one of said first and second transistors for one signal condition and for turning-on the other one of said first and second transistors for a complementary signal condition; means adapted to receive clock signals having one value during a first time interval and a second value during a second time interval; and means adapted to receive the complement of said clock signals; and means for applying said clock signals to said first terminal and the complement of said clock signals to said second terminal; said diodes being poled for during said first time interval allowing power to be supplied from said clock signals and said complementary clock signals to said first and second paths for producing a current responsive to said data input means in one of said two paths and producing a corresponding charge at said output node and for during a second time interval said diodes being poled to prevent the flow of current through said paths for preventing the charge at said output node from changing during said second time interval.

Claim 11

The combination comprising: first and second field effect transistors having a conduction path through which current can flow bidirectionally and a control electrode; a first path comprising the conduction path of said first transisTor connected in series with a first diode between a first terminal and a capacitive output node; said first diode being poled to allow conduction in only one direction through said first transistor; a second path comprising the conduction path of said second transistor connected in series with a second diode between a second terminal and said output node; said second diode being poled to allow conduction in only one direction through said second transistor; data input means connected to the control electrode of said two transistors for turning-on one of said first and second transistors for one signal condition and for turning-on the other one of said first and second transistors for a complementary signal condition; means adapted to receive clock signals having one value during a first time interval and a second value during a second time interval; and means adapted to receive the complement of said clock signals; and means for applying said clock signals to said first terminal and the complement of said clock signals to said second terminal; said diodes being poled for during said first time interval allowing power to be supplied from said clock signals and said complementary clock signals to said first and second paths for producing a current responsive to said data input means in one of said two paths and producing a corresponding charge at said output node and for during a second time interval said diodes being poled to prevent the flow of current through said paths for preventing the charge at said output node from changing during said second time interval.