Counter or shift register stage having both static and dynamic storage circuits

Claim 1

A signal translating stage operable during first and second consecutive time intervals to translate information signals from the input terminal to the output terminal of said stage comprising: means providing a clock signal having first and second successive and nonoverlapping time intervals during which it is at different voltage levels; first, second and third semiconductor inverter devices, said first and second inverter device cross-coupled to form a flipflop and having an input terminal and an output terminal to thereby form a first storage circuit for statically storing said information; a second storage circuit responsive to and in cooperation with said clock signal for storing charge dynamically, consisting solEly of said third inverter device having an output terminal and an input terminal which exhibits a predominantly capacitive, relatively high input impedance; first transmission gate means responsive to said clock signal for coupling the input terminal of said stage to the input terminal of one of said storage circuits only during said first time intervals; second transmission gate means responsive to said clock signal for coupling the output terminal of said one storage circuit to the input terminal of the other storage circuit only during said second time intervals; and means for coupling the output terminal of said other storage circuit to the output terminal of the stage.