US3577166A
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US
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C-mos dynamic binary counter
Assignee: RCA Corp
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Filing: 1968-09-17
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Granted: 1971-05-04
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Expires: 1988-09-17
Abstract
Abstract A dynamic flip-flop comprising two inverter means and two switching means is described. The switching means couple, by different conduction paths, the input node of one inverter means to the input node and to the output means of the other inverter. The switching means are alternately enabled by a clocking signal varying at a first rate causing the signals at the inputs and outputs of both inverter means to vary at one half said first rate. The temporary or momentary storage provided by the capacitance at the input node of an inverter stage, coupled with the single pole, double throw action of the switching means, enables the design of a dynamic binary counter using a minimum number of components.
Inventors
- 👤 Abraham K Yung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:23
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
59 words
The combination comprising first and second means, each having an input node and an output means; first switching means connected between the input node of the first inverter means and the input node of the second inverter means; and second switching means connected between the output means of the first inverter and the input node of the second inverter.
Claim 2
Dependent Claim
59 words
The combination comprising first and second means, each having an input node and an output means; first switching means connected between the input node of the first inverter means and the input node of the second inverter means; and second switching means connected between the output means of the first inverter and the input node of the second inverter.
Claim 3
Dependent Claim
20 words
In the combination set forth in claim 1, each inverter means including at its input mode a charge storage means.
Claim 4
Dependent Claim
17 words
The combination as claimed in claim 2, wherein said first and second switching means are alternately enabled.
Claim 5
Dependent Claim
63 words
The combination as claimed in claim 2, further including first and second terminal points; means connecting the first and second inverter means in parallel between said terminal points; wherein each switching means comprises A pair of transistors, one transistor being of one conductivity type and the other of opposite conductivity type; and means for connecting a source of potential between said terminal points.
Claim 6
Dependent Claim
108 words
The combination as claimed in claim 4, wherein each transistor has first and second electrodes defining the ends of a conduction path and a control electrode; wherein each inverter comprises a pair of transistors of different conductivity type; wherein the two transistors of the first inverter means have their control electrodes connected to said first input node; wherein the two transistors of the second inverter means have their control electrodes connected to said second input node and one end of their conduction paths connected in common at said second output means; and wherein the two transistors of the first switching means have their conduction paths connected in parallel.
Claim 7
Dependent Claim
66 words
The combination as claimed in claim 5; wherein the two transistors of the first inverter means have one end of their conduction paths connected in common at said first output means; and wherein the two transistors of the second switching means have their conduction paths connected in parallel between said input node of the second inverter means and the output means of the first inverter means.
Claim 8
Dependent Claim
151 words
The combination as claimed in claim 5; wherein one of the two transistors of the second switching means has one end of its conduction path connected to one end of the conduction path of one of the two transistors of the first inverter means and the other transistor of the second switching means has one end of its conduction path connected to one end of the conduction path of the other transistor of the first inverter means, and the other ends of the conduction paths of the switching means transistors being connected in common to the input node of the second inverter means; and wherein the other end of the conduction path of one transistor of the first inverter means is connected to the first terminal point, and the other end of the conduction path of the other transistor of the first inverter means is connected to the second terminal point.
Claim 9
Dependent Claim
14 words
The combination as claimed in claim 4, wherein the transistors are insulated-gate field-effect transistors.
Claim 10
Dependent Claim
88 words
The combination as claimed in claim 4, further including means for applying an alternating signal and its complement to said switching means; and wherein said alternating signal is applied to the control electrodes of the one conductivity-type transistor of the first switching means and to the opposite conductivity-type transistor of the second switching means and the complement of said alternating signal is applied to the control electrodes of the opposite conductivity-type transistor of the first switching means and to the one conductivity-type transistor of the second switching means.
Claim 11
Dependent Claim
78 words
The combination as claimed in claim 1 further including clock signal means coupled to said first and second switching means for enabling said first switching means and disabling said second switching means during a first time interval, and for disabling said first switching means and enabling said second switching means during a second time interval; each first time interval being succeeded by said second time interval and each second time interval being succeeded by said first time interval.
Claim 12
Dependent Claim
140 words
A counter stage comprising: first and second inverter means each having an input mode and an output means; first switching means for connecting the output means of the first inverter means to the input node of the second inverter means only during a first time interval for transferring the signal at said output means of said first inverter means to the input node of said second inverter means; and second switching means for connecting the input node of the second inverter means to the input node of the first inverter means only during a second time interval succeeding said first time interval foR transferring a portion of the signal derived from the output means of said first inverter means and now present at the input node of said second inverter means to the input node of said first inverter means.
Claim 13
Dependent Claim
140 words
A counter stage comprising: first and second inverter means each having an input mode and an output means; first switching means for connecting the output means of the first inverter means to the input node of the second inverter means only during a first time interval for transferring the signal at said output means of said first inverter means to the input node of said second inverter means; and second switching means for connecting the input node of the second inverter means to the input node of the first inverter means only during a second time interval succeeding said first time interval foR transferring a portion of the signal derived from the output means of said first inverter means and now present at the input node of said second inverter means to the input node of said first inverter means.
Claim 14
Dependent Claim
120 words
In combination: first and second logical inverter means, each having an input terminal and an output terminal; first and second charge storage means, the first connected between the input terminal of said first inverter means and a source of reference potential and the second connected between the input terminal of the second inverter means and said source of reference potential; means connecting the output terminal of the first inverter means to the input terminal of the second inverter means during one time interval; and means for opening the connection between said output and input terminal and concurrently connecting the input terminal of said second inverter means to the input terminal of said first inverter means, during a second time interval.
Claim 15
Dependent Claim
120 words
In combination: first and second logical inverter means, each having an input terminal and an output terminal; first and second charge storage means, the first connected between the input terminal of said first inverter means and a source of reference potential and the second connected between the input terminal of the second inverter means and said source of reference potential; means connecting the output terminal of the first inverter means to the input terminal of the second inverter means during one time interval; and means for opening the connection between said output and input terminal and concurrently connecting the input terminal of said second inverter means to the input terminal of said first inverter means, during a second time interval.
Claim 16
Dependent Claim
17 words
In the combination as set forth in claim 12, each charge storage means comprising a distributed capacitance.
Claim 17
Dependent Claim
65 words
In the combination as set forth in claim 13, each inverter means comprising a pair of complementary symmetry field-effect transistors, the conduction paths of which are connected in series, the input terminal of which comprises a common connection to the gate electrodes of said pair of transistors, and the output terminal of which comprises the connection between the conduction paths of said pair of transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-03 | 1974-11-02 | 1975-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-03 | 1978-11-02 | 1979-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-03 | 1982-11-02 | 1983-05-04 | $7700.00 | Window Closed / Lapsed |