US5483497A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory having a plurality of banks usable in a plurality of bank configurations
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1994-07-19
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Granted: 1996-01-09
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Expires: 2014-07-19
Abstract
Abstract A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.
Inventors
- 👤 Hirohiko Mochizuki
- 👤 Yoshihiro Takemae
- 👤 Yukinori Kodama
- 👤 Makoto Yanagisawa
- 👤 Katsumi Shigenobu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:54
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G11; G11C; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C8/10; G11C8/18
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
122 words
A semiconductor memory comprising: a plurality of banks, each of said banks having a plurality of memory cells, and a specific memory cell of a specific bank being selected in accordance with a first address signal and a second address signal successively provided to said semiconductor memory; a first specify means for specifying one of said plurality of banks by decoding a bank address signal contained in said first address signal; and a second specify means or specifying one of said plurality of banks by decoding the bank address signal contained in said first address signal, according to bank status signals indicating whether or not each of said banks is activated, so that said semiconductor memory is used for different bank configurations.
Claim 2
Dependent Claim
122 words
A semiconductor memory comprising: a plurality of banks, each of said banks having a plurality of memory cells, and a specific memory cell of a specific bank being selected in accordance with a first address signal and a second address signal successively provided to said semiconductor memory; a first specify means for specifying one of said plurality of banks by decoding a bank address signal contained in said first address signal; and a second specify means or specifying one of said plurality of banks by decoding the bank address signal contained in said first address signal, according to bank status signals indicating whether or not each of said banks is activated, so that said semiconductor memory is used for different bank configurations.
Claim 3
Dependent Claim
18 words
A semiconductor memory as claimed in claim 1, wherein said semiconductor memory is a dynamic random access memory.
Claim 4
Dependent Claim
21 words
A semiconductor memory as claimed in claim 2, wherein said dynamic random access memory is a synchronous dynamic random access memory.
Claim 5
Dependent Claim
43 words
A semiconductor memory as claimed in claim 3, wherein a bank activation instruction and a read instruction are provided with a clock enable signal, a chip select signal, a row address strobe signal, a column address strobe signal, and a write enable signal.
Claim 6
Dependent Claim
20 words
A semiconductor memory as claimed in claim 1, wherein said plurality of drivers drive corresponding word decoders and sense amplifiers.
Claim 7
Dependent Claim
30 words
A semiconductor memory as claimed in claim 1, wherein said banks maintain an active state if required even under an unselected state after a read operation or a write operation.
Claim 8
Dependent Claim
28 words
A semiconductor memory as claimed in claim 1, wherein said first address signal is a row address signal, and said second address signal is a column address signal.
Claim 9
Dependent Claim
82 words
A semiconductor memory as claimed in claim 1, wherein the number of said banks are determined to 2 x , where x is an integer equal to or greater than two; said bank configurations include a first bank configuration and a second bank configuration, said first bank configuration being 2 x and said second bank configuration being 2 y , where y is an integer equal to or greater than one and obtained by dividing the x by a multiple of two.
Claim 10
Dependent Claim
135 words
A semiconductor memory as claimed in claim 8, wherein said first specify means decodes an x-bit bank address signal contained in said first address signal, to specify one of said 2 x banks functioning as they are or as 2 y banks; and said second specify means decodes, according to said bank status signals indicating whether or not each of said 2 x banks is active, an x-bit bank address signal contained in said second address signal if said 2 x banks function as they are or a y-bit bank address signal contained in said second address signal if said 2 x banks function as 2 y banks, to specify the bank that has been specified according to said first address signal, so that data are written into or read out of said specified bank.
Claim 11
Dependent Claim
226 words
A semiconductor memory having 2 x banks, where x is an integer equal to or greater than two, that maintain an active state if required even under an unselected state after a read or write operation, any memory cell in any one of said banks being selectable according to a first address signal and a second address signal successively provided to said semiconductor memory, wherein said semiconductor memory comprises: a first specify means for decoding an x-bit bank address signal contained in said first address signal, to specify one of said 2 x banks functioning as they are or as 2 y banks, where y is an integer equal to or greater than one and obtained by dividing the x by a multiple of two, so that a word line is selected in said specified bank; and a second specify means for decoding, according to indicating whether or not each of said 2 x banks is active, an x-bit bank address signal contained in said second address signal if said 2 x banks function as they are or a y-bit bank address signal contained in said second address signal if said 2 x banks functional as 2 y banks, to specify the bank that has been specified according to said first address signal, so that data are written into or read out of said specified bank.
Claim 12
Dependent Claim
226 words
A semiconductor memory having 2 x banks, where x is an integer equal to or greater than two, that maintain an active state if required even under an unselected state after a read or write operation, any memory cell in any one of said banks being selectable according to a first address signal and a second address signal successively provided to said semiconductor memory, wherein said semiconductor memory comprises: a first specify means for decoding an x-bit bank address signal contained in said first address signal, to specify one of said 2 x banks functioning as they are or as 2 y banks, where y is an integer equal to or greater than one and obtained by dividing the x by a multiple of two, so that a word line is selected in said specified bank; and a second specify means for decoding, according to indicating whether or not each of said 2 x banks is active, an x-bit bank address signal contained in said second address signal if said 2 x banks function as they are or a y-bit bank address signal contained in said second address signal if said 2 x banks functional as 2 y banks, to specify the bank that has been specified according to said first address signal, so that data are written into or read out of said specified bank.
Claim 13
Dependent Claim
18 words
A semiconductor memory as claimed in claim 10, wherein said semiconductor memory is a dynamic random access memory.
Claim 14
Dependent Claim
21 words
A semiconductor memory as claimed in claim 11, wherein said dynamic random access memory is a synchronous dynamic random access memory.
Claim 15
Dependent Claim
43 words
A semiconductor memory as claimed in claim 12, wherein a bank activation instruction and a read instruction are provided with a clock enable signal, a chip select signal, a row address strobe signal, a column address strobe signal, and a write enable signal.
Claim 16
Dependent Claim
20 words
A semiconductor memory as claimed in claim 10, wherein said plurality of drivers drive corresponding word decoders and sense amplifiers.
Claim 17
Dependent Claim
30 words
A semiconductor memory as claimed in claim 10, wherein said banks maintain an active state if required even under an unselected state after a read operation or a write operation.
Claim 18
Dependent Claim
28 words
A semiconductor memory as claimed in claim 10, wherein said first address signal is a row address signal, and said second address signal is a column address signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |