US4884270A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Easily cascadable and testable cache memory
Assignee: Texas Instruments Inc
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Filing: 1988-10-14
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Granted: 1989-11-28
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Expires: 2008-10-14
Abstract
Abstract The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory call array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.
Inventors
- 👤 Edison H. Chiu
- 👤 Roland H. Pang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
111 words
A single semiconductor chip cache memory comprising: (a) a SRAM having plural data inputs, plural address inputs, plural address locations for storing data and plural data outputs; (b) a comparator for comparing said data inputs stored at said addressed locations to provide a comparator output indicative of a match between input and stored data; and (c) an output transistor having three electrodes including first and second electrodes and a control electrode for selectively coupling together the first and second electrodes, said control electrode being coupled to the comparator output to control the coupling or uncoupling of the first and second terminals in response to the comparator output at the control terminal.
Claim 2
Dependent Claim
111 words
A single semiconductor chip cache memory comprising: (a) a SRAM having plural data inputs, plural address inputs, plural address locations for storing data and plural data outputs; (b) a comparator for comparing said data inputs stored at said addressed locations to provide a comparator output indicative of a match between input and stored data; and (c) an output transistor having three electrodes including first and second electrodes and a control electrode for selectively coupling together the first and second electrodes, said control electrode being coupled to the comparator output to control the coupling or uncoupling of the first and second terminals in response to the comparator output at the control terminal.
Claim 3
Dependent Claim
32 words
A cache memory as set forth in claim 1 wherein the transistor comprises a field effect transistor having a gate coupled to the output of the comparator and an open drain electrode.
Claim 4
Dependent Claim
19 words
A cache memory as set forth in claim 2 wherein the transistor source is connected to a reference voltage.
Claim 5
Dependent Claim
37 words
A cache memory as set forth in claim 1 further comprising a parity checker reponsive to the addressed stored data and to the input data for checking the parity of said stored data with said input data.
Claim 6
Dependent Claim
51 words
A cache memory as set forth on claim 4 further comprising a parity generator responsive to said data input for providing an output indicative of the parity thereof and a gate responsive to the output of said parity generator and the output of said parity checker to provide a parity input.
Claim 7
Dependent Claim
17 words
A cache memory as set forth in claim 5 wherein said gate is an exclusive OR circuit.
Claim 8
Dependent Claim
157 words
A cache memory system comprising: (a) a plurality of semiconductor cache memory chips, each of said chips comprising: (b) a SRAM having plural data inputs, plural address inputs, plural data locations and plural data outputs; (c) a comparator for comparing said data inputs to data stored at an addressed location to provide a comparator output indicative of a match in said comparator; (d) an output transistor having three electrodes including first and second electrodes and a control electrode for selectively coupling together the first and second electrodes, said control electrode being coupled to the comparator output to control the coupling or uncoupling of the first and second terminals in response to said comparator output at said control terminal; (e) a processor data bus coupled to the data inputs of each of said chips; (f) a processor address bus coupled to the data inputs of each of said chips; wherein said first or second electrodes are coupled together.
Claim 9
Dependent Claim
157 words
A cache memory system comprising: (a) a plurality of semiconductor cache memory chips, each of said chips comprising: (b) a SRAM having plural data inputs, plural address inputs, plural data locations and plural data outputs; (c) a comparator for comparing said data inputs to data stored at an addressed location to provide a comparator output indicative of a match in said comparator; (d) an output transistor having three electrodes including first and second electrodes and a control electrode for selectively coupling together the first and second electrodes, said control electrode being coupled to the comparator output to control the coupling or uncoupling of the first and second terminals in response to said comparator output at said control terminal; (e) a processor data bus coupled to the data inputs of each of said chips; (f) a processor address bus coupled to the data inputs of each of said chips; wherein said first or second electrodes are coupled together.
Claim 10
Dependent Claim
32 words
A cache memory as set forth in claim 7 wherein the transistor comprises a field effect transistor having a gate coupled to the output of the comparator and an open drain electrode.
Claim 11
Dependent Claim
19 words
A cache memory as set forth in claim 8 wherein the transistor source is connected to a reference voltage.
Claim 12
Dependent Claim
37 words
A cache memory as set forth in claim 7 further comprising a parity checker responsive to the addressed stored data and to the input data for checking the parity of said stored data with said input data.
Claim 13
Dependent Claim
51 words
A cache memory as set forth on claim 10 further comprising a parity generator responsive to said data input for providing an output indicative of the parity thereof and a gate responsive to the output of said parity generator and the output of said parity checker to provide a parity input.
Claim 14
Dependent Claim
17 words
A cache memory as set forth in claim 11 wherein said gate is an exclusive OR circut.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |