Random access memory having flash memory

Claim 2

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, and a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time.

Claim 3

A semiconductor nonvolatile memory device as set forth in claim 1, wherein said nonvolatile memory comprises a plurality of memory cell blocks connected to said first and second bit lines, and selection transistors are connected in cascade in two stages between said memory cell blocks and said first and second bit lines and selection gates of the selection transistors are connected to a common selection gate line to selectively connect said memory cell blocks to said first and second bit lines.

Claim 4

A semiconductor nonvolatile memory device as set forth in claim 1, wherein said memory device comprises at least two buffer memories and nonvolatile memories.

Claim 5

A semiconductor nonvolatile memory device as set forth in claim 1, wherein the capacity of said buffer memory is set to a whole multiple of the size of the page to be written at one time in said nonvolatile memory.

Claim 6

A semiconductor nonvolatile memory device as set forth in claim 1, wherein said buffer memory comprises a static RAM.

Claim 7

A semiconductor nonvolatile memory device as set forth in claim 5, wherein when a power source is energized, the data is written into and read from said static RAM and when said power source is deenergized, the data held in said static RAM is evacuated to said nonvolatile memory.

Claim 8

A semiconductor nonvolatile memory device as set forth in claim 1, wherein the buffer memory comprises a dynamic RAM.

Claim 9

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, and a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time, and wherein said memory device comprises at least two buffer memories and nonvolatile memories.

Claim 10

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, and a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time, and wherein said memory device comprises at least two buffer memories and nonvolatile memories.

Claim 11

A semiconductor nonvolatile memory device as set forth in claim 8, wherein said buffer memory comprises a static RAM.

Claim 12

A semiconductor nonvolatile memory device as set forth in claim 9, wherein when a power source is energized, the data is written into and read from said static RAM and when said power source is deenergized, the data held in said static RAM is evacuated to said nonvolatile memory.

Claim 13

A semiconductor nonvolatile memory device as set forth in claim 8, wherein the buffer memory comprises a dynamic RAM.

Claim 14

A semiconductor nonvolatile memory device as set forth in claim 8, wherein said nonvolatile memory comprises a plurality of memory cell blocks connected to said first and second bit lines, and selection transistors are connected in cascade in two stages between said memory cell blocks and said first and second bit lines and selection gates of the selection transistors are connected to a common selection gate line to selectively connect said memory cell blocks to said first and second bit lines.

Claim 15

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein the buffer memory and the nonvolatile memory are each of a folded bit line type memory configuration and both memories are connected through the same bit line; and wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, and a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time.

Claim 16

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein the buffer memory and the nonvolatile memory are each of a folded bit line type memory configuration and both memories are connected through the same bit line; and wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, and a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time.

Claim 17

A semiconductor nonvolatile memory device as set forth in claim 13, wherein said memory device comprises at least two buffer memories and nonvolatile memories.

Claim 18

A semiconductor nonvolatile memory device as set forth in claim 13, wherein the capacity of said buffer memory is set to a whole multiple of the size of the page to be written at one time in said nonvolatile memory.

Claim 19

A semiconductor nonvolatile memory device as set forth in claim 13, wherein said buffer memory comprises a static RAM.

Claim 20

A semiconductor nonvolatile memory device as set forth in claim 16, wherein when a power source is energized, the data is written into and read from said static RAM and when said power source is deenergized, the data held in said static RAM is evacuated to said nonvolatile memory.

Claim 21

A semiconductor nonvolatile memory device as set forth in claim 13, wherein the buffer memory comprises a dynamic RAM.

Claim 22

A semiconductor nonvolatile memory device as set forth in claim 13, wherein: said nonvolatile memory comprises a plurality of memory cell blocks connected to said first and second bit lines, and selection transistors are connected in cascade in two stages between said memory cell blocks and said first and second bit lines and selection gates of the selection transistors are connected to a common selection gate line to selectively connect said memory cell blocks to said first and second bit lines.

Claim 23

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein the buffer memory and the nonvolatile memory are each of a folded bit line type memory configuration and both memories are connected through the same bit line; wherein said memory device comprises at least two buffer memories and nonvolatile memories; and wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time.

Claim 24

A semiconductor nonvolatile memory device comprising: a first bit line; a second bit line; a buffer memory connected to said first and second bit lines; an electrically erasable programmable nonvolatile memory connected to said first and second bit lines; a writing latch circuit to which said first and second bit lines are connected in parallel and having a differential sensor type sense amplifier; a switching circuit for switching said nonvolatile memory and said writing latch circuit to a nonconnected state when said buffer memory is in operation, and switching said buffer memory and said writing latch circuit to a nonconnected state when said nonvolatile memory is in a writing or erasure operation; wherein the buffer memory and the nonvolatile memory are each of a folded bit line type memory configuration and both memories are connected through the same bit line; wherein said memory device comprises at least two buffer memories and nonvolatile memories; and wherein said nonvolatile memory comprises: a first memory cell connected to a word line and said first bit line, a second memory cell connected to a word line common with said first memory cell and connected to said second bit line, a means for holding the potential of either of said first and second bit lines at a first potential at a predetermined operation time and for setting the potential of the other bit line of said first and second bit lines to a second potential given a difference with the first potential for a predetermined time.

Claim 25

A semiconductor nonvolatile memory device as set forth in claim 20, wherein said buffer memory comprises a static RAM.

Claim 26

A semiconductor nonvolatile memory device as set forth in claim 21, wherein when a power source is energized, the data is written into and read from said static RAM and when said power source is deenergized, the data held in said static RAM is evacuated to said nonvolatile memory.

Claim 27

A semiconductor nonvolatile memory device as set forth in claim 20, wherein the buffer memory comprises a dynamic RAM.

Claim 28

A semiconductor nonvolatile memory device as set forth in claim 20, wherein: said nonvolatile memory comprises a plurality of memory cell blocks connected to said first and second bit lines, and selection transistors are connected in cascade in two stages between said memory cell blocks and said first and second bit lines and selection gates of the selection transistors are connected to a common selection gate line to selectively connect said memory cell blocks to said first and second bit lines.