US5638335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: PS4 Luxco SARL
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Filing: 1996-05-17
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Granted: 1997-06-10
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Expires: 2016-05-17
Abstract
Abstract A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.
Inventors
- 👤 Noboru Akiyama
- 👤 Seigoh Yukutake
- 👤 Sadayuki Ohkuma
- 👤 Akihiko Emori
- 👤 Takashi Akioka
- 👤 Shuichi Miyaoka
- 👤 Shinji Nakazato
- 👤 Kinya Mitsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:31
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C7/00; G11C7/06; G11C7/062; G11C7/10; G11C7/1048; G11C7/1051; G11C7/1069; G11C7/1078; G11C7/1096
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
64 words
A semiconductor memory comprising: a memory array having a plurality of bits including parity bits, and comprising a plurality of memory blocks; and a bit structure changing section for changing the input/output bits of said memory array, wherein the number of said memory blocks is an integral multiple of three and the number of input/output bits of said plurality of memory blocks is even.
Claim 2
Dependent Claim
64 words
A semiconductor memory comprising: a memory array having a plurality of bits including parity bits, and comprising a plurality of memory blocks; and a bit structure changing section for changing the input/output bits of said memory array, wherein the number of said memory blocks is an integral multiple of three and the number of input/output bits of said plurality of memory blocks is even.
Claim 3
Dependent Claim
40 words
A semiconductor memory as claimed in claim 1, wherein a peripheral circuit is provided at the center of a central memory block, which is located at the center of a chip and forms one of said plurality of memory blocks.
Claim 4
Dependent Claim
112 words
A semiconductor memory comprising: a memory array having a plurality of bits including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of said memory array, said bit structure changing section being provided with: (a) an I/O selector for selecting one bit structure from a plurality of bit structures, and (b) a data selector responsive to an output signal from said I/O selector for changing the data input bits or the data output bits, wherein the number of said memory blocks is an integral multiple of three and the number of input/output bits of said plurality of memory blocks is even.
Claim 5
Dependent Claim
112 words
A semiconductor memory comprising: a memory array having a plurality of bits including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of said memory array, said bit structure changing section being provided with: (a) an I/O selector for selecting one bit structure from a plurality of bit structures, and (b) a data selector responsive to an output signal from said I/O selector for changing the data input bits or the data output bits, wherein the number of said memory blocks is an integral multiple of three and the number of input/output bits of said plurality of memory blocks is even.
Claim 6
Dependent Claim
37 words
A semiconductor memory as claimed in claim 3, wherein said data selector has at least a write amplifier for writing data to a memory cell and a sense amplifier for amplifying data outputted from a memory cell.
Claim 7
Dependent Claim
38 words
A semiconductor memory as claimed in claim 4, wherein said data selector has at least a column select switch for connecting or disconnecting bit lines connected to memory cells with or from said write amplifier and sense amplifier.
Claim 8
Dependent Claim
40 words
A semiconductor memory as claimed in claim 3, wherein a peripheral circuit is provided at the center of a central memory block which is located at the center of a chip and forms one of said plurality of memory blocks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |