Patent US1587668A successfully refreshed from Google Patents.
EP0450871A2
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Interfaces for transmission lines
Assignee: Xerox Corp
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Filing: 1991-03-28
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Granted: —
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Expires: 2011-03-28
Abstract
Abstract This invention provides very wide channel, open drain, N-channel CMOS drivers (16) and cascode CMOS receivers (17) for interfacing VLSI CMOS circuits to transmission lines (14) which are terminated by their characteristic resistive impedances (21, 22) to voltage levels of the order of about 1.2 - 2.0 V. These GTL (a coined descriptor) drivers and receivers typically operate with a voltage swing of the order of about 0.8 - 1.4 V on such transmission lines for carrying out binary communications between CMOS circuits configured to operate with standard 5 V rail-to-rail voltage swings for their internal signals.
Inventors
- 👤 William F. Gunning
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 19:39
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/018571
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
129 words
An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line (14) for binary communications between the circuits at signal levels providing a signal swing of about 0.8 - 1.4 V between a line-terminating voltage level of about 1.2 - 2.0 V and a low voltage level of about 0.4 - 0.6 V; the interface comprising drivers (16) for feeding binary signals from CMOS circuits (26) to a transmission line (14); each driver including an N-channel transistor (25) having a drain coupled to the transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of the CMOS circuits; the gate of the transistor being of chosen effective width and length, with its width being many times greater than its length.
Claim 2
Dependent Claim
146 words
The interface of Claim 1 further comprising receivers (17) for feeding binary signals from the transmission line to the CMOS circuits, each receiver including a N-channel transistor (28), a P-channel transistor (27), means for supplying a reference voltage, and means for supplying a bias voltage; the N-channel transistor having a source coupled to the transmission line, a drain, and a gate coupled to the reference voltage; the P-channel transistor having a source coupled to a power supply, a drain coupled to the drain of the N-channel transistor, and a gate coupled to the bias voltage; the bias voltage being selected to bias the P-channel transistor for conduction; and the reference voltage being selected for switching the N-channel transistor into and out of conduction as the signal on the transmission line drops below and rises above, respectively, a decision threshold near the center of the signal swing.
Claim 3
Dependent Claim
55 words
The interface of Claim 2, wherein receiver further includes an amplifier coupled to the drains of the transistors; and a flip-flop coupled to the amplifier, the flip-flop being prepared to switch from one state to another when the signal on the transmission line drops below and rises above, the decision threshold by a chosen amount.
Claim 4
Dependent Claim
124 words
An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line (14) for binary communications between the circuits at signal levels providing a nominal signal swing of up to about 1 .4V between a line terminating voltage level of up to about 2.0V and a lower voltage level; the interface comprising drivers (16) for feeding binary signals from the CMOS circuits (26) to the transmission line; each driver including an N-channel transistor (28) having a drain coupled to the transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of the CMOS circuits; the gate of the transistor being of chosen effective width and length, with its width being many times greater than its length.
References Cited (Backward Citations)
No citation records indexed.
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