US5636173A
Expired / Lapsed
US
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Auto-precharge during bank selection
Assignee: Round Rock Research LLC
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Filing: 1995-06-07
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Granted: 1997-06-03
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Expires: 2015-06-07
Abstract
Abstract A synchronous dynamic random access memory (SDRAM) is responsive to command signals and includes a first bank memory array and a second bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an active command controlling an active operation on the first bank memory array and to initiate, in a second system clock cycle, a transfer read or write command controlling a read or write transfer operation for transferring data from or to the first bank memory array. The command controller responds to the active command to automatically initiate, in the second system clock cycle, a precharge command controlling a precharge operation on the second bank memory array.
Inventors
- 👤 Scott Schaefer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:50
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04; G11C7/00; G11C7/10; G11C7/1072; G11C7/12
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
148 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a first bank memory array having storage cells organized in rows and columns for storing dam; a second bank memory array having storage cells organized in rows and columns for storing dam; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a first command controlling a first operation on the first bank memory array and to initiate, at a second active edge of the system clock, a transfer command controlling a transfer operation for transferring dam to or from the first bank memory array, and responsive to the fist command to automatically initiate at the second active edge of the system clock, a third command controlling a third operation on the second bank memory array.
Claim 2
Dependent Claim
148 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a first bank memory array having storage cells organized in rows and columns for storing dam; a second bank memory array having storage cells organized in rows and columns for storing dam; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a first command controlling a first operation on the first bank memory array and to initiate, at a second active edge of the system clock, a transfer command controlling a transfer operation for transferring dam to or from the first bank memory array, and responsive to the fist command to automatically initiate at the second active edge of the system clock, a third command controlling a third operation on the second bank memory array.
Claim 3
Dependent Claim
34 words
The memory device of claim 1 further comprising a mode register for storing mode information, wherein the command decoder/controller initiates the third command in response to the first command based on the mode information.
Claim 4
Dependent Claim
12 words
The memory device of claim 2 wherein the mode register is programmable.
Claim 5
Dependent Claim
47 words
The memory device of claim 1 wherein the first command is an active command and wherein the first operation includes latching a value representing a row address of the first bank memory array and activating the addressed row of storage cells in the first bank memory array.
Claim 6
Dependent Claim
42 words
The memory device of claim 4 wherein the third command is initiated based on the active command to the first bank memory array being initiated during a second bank transfer operation for transferring data to or from the second bank memory array.
Claim 7
Dependent Claim
59 words
The memory device of claim 4 wherein the active command is a special type of two types of active commands including a special type and a normal type, wherein the normal type active command does not trigger the automatic initiation of the third command, and the special type active command does trigger the automatic initiation of the third command.
Claim 8
Dependent Claim
28 words
The memory device of claim 1 wherein the third command is a precharge command and wherein the third operation includes precharging and deactivating the second bank memory array.
Claim 9
Dependent Claim
30 words
The memory device of claim 1 wherein the transfer command is a read command and the transfer operation reads data from a storage cell in the first bank memory array.
Claim 10
Dependent Claim
30 words
The memory device of claim 1 wherein the transfer command is a write command and the transfer operation writes data to a storage cell in the first bank memory array.
Claim 11
Dependent Claim
17 words
The memory device of claim 1 wherein the memory device is a synchronous dynamic random access memory.
Claim 12
Dependent Claim
38 words
The memory device of claim 1 wherein the memory device comprises more than two bank memory arrays, and wherein the second bank memory array is predefined as a closest bank memory array to the first bank memory array.
Claim 13
Dependent Claim
46 words
The memory device of claim 1 wherein the memory device comprises more than two bank memory arrays, and wherein the second bank memory array is the most recently accessed bank memory array prior to the initiation of the transfer command to the first bank memory array.
Claim 14
Independent Claim
124 words
A method of initiating commands in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a first command controlling a first operation on a first bank memory array; initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation for transferring data to or from the first bank memory array; and automatically initiating, at the second active edge of the system clock, in response to the first command, a third command controlling a third operation on a second bank memory array.
Claim 15
Independent Claim
124 words
A method of initiating commands in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a first command controlling a first operation on a first bank memory array; initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation for transferring data to or from the first bank memory array; and automatically initiating, at the second active edge of the system clock, in response to the first command, a third command controlling a third operation on a second bank memory array.
Claim 16
Dependent Claim
49 words
The method of claim 13 wherein the first command is an active command and wherein the first operation includes the steps of latching a value representing a row address of the first bank memory array and activating the addressed row of storage cells in the fast bank memory array.
Claim 17
Dependent Claim
41 words
The method of claim 14 wherein the third command is initiated based on the active command to the fast bank memory array being initiated during a second bank transfer operation for transferring data to or from the second bank memory array.
Claim 18
Dependent Claim
58 words
The method of claim 14 wherein the active command is a special type of two types of active commands including a special type and a normal type, wherein the normal type active command does not trigger the automatic initiation of the third command, and the special type active command does trigger the automatic initiation of the third command.
Claim 19
Dependent Claim
30 words
The method of claim 13 wherein the third command is a precharge command and wherein the third operation includes the steps of precharging and deactivating the second bank memory array.
Claim 20
Dependent Claim
33 words
The method of claim 13 wherein the transfer command is a read command and the transfer operation includes the step of reading data from a storage cell in the first bank memory array.
Claim 21
Dependent Claim
33 words
The method of claim 13 wherein the transfer command is a write command and the transfer operation includes the step of writing data to a storage cell in the first bank memory array.
Claim 22
Dependent Claim
43 words
The method of claim 13 wherein the memory device comprises more than two bank memory arrays, and wherein the method further comprises the step of predefining the second bank memory array as a closest bank memory array to the first bank memory array.
Claim 23
Dependent Claim
45 words
The method of claim 13 wherein the memory device comprises more than two bank memory arrays, and wherein the second bank memory array is the most recently accessed bank memory array prior to the initiation of the transfer command to the first bank memory array.
Claim 24
Dependent Claim
145 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a first bank memory array having storage cells organized in rows and columns for storing data; a second bank memory array having storage cells organized in rows and columns for storing dam; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, an active command controlling an active operation which includes latching a value representing a row address of the first bank memory array and activating the addressed row of storage cells in the first bank memory array, and responsive to the active command to automatically initiate at a second active edge of the system clock, a precharge command controlling a precharge operation which includes precharging and deactivating the second bank memory array.
Claim 25
Dependent Claim
145 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a first bank memory array having storage cells organized in rows and columns for storing data; a second bank memory array having storage cells organized in rows and columns for storing dam; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, an active command controlling an active operation which includes latching a value representing a row address of the first bank memory array and activating the addressed row of storage cells in the first bank memory array, and responsive to the active command to automatically initiate at a second active edge of the system clock, a precharge command controlling a precharge operation which includes precharging and deactivating the second bank memory array.
Claim 26
Dependent Claim
45 words
The memory device of claim 22 wherein the command decoder/controller is responsive to selected command signals to initiate, at the second active edge of the system clock, a transfer command controlling a transfer operation for transferring data to or from the fast bank memory array.
Claim 27
Dependent Claim
30 words
The memory device of claim 23 wherein the transfer command is a read command and the transfer operation reads data from a storage cell in the first bank memory array.
Claim 28
Dependent Claim
30 words
The memory device of claim 23 wherein the transfer command is a write command and the transfer operation writes data to a storage cell in the first bank memory array.
Claim 29
Dependent Claim
34 words
The memory device of claim 22 further comprising a mode register for storing mode information, wherein the command controller initiates the precharge command in response to the active command based on the mode information.
Claim 30
Dependent Claim
12 words
The memory device of claim 26 wherein the mode register is programmable.
Claim 31
Dependent Claim
42 words
The memory device of claim 22 wherein the precharge command is initiated based on the active command to the first bank memory array being initiated during a second bank transfer operation for transferring data to or from the second bank memory array.
Claim 32
Dependent Claim
59 words
The memory device of claim 22 wherein the active command is a special type of two types active of commands including a special type and a normal type, wherein the normal type active command does not trigger the automatic initiation of the precharge command, and the special type active command does trigger the automatic initiation of the precharge command.
Claim 33
Dependent Claim
17 words
The memory device of claim 22 wherein the memory device is a synchronous dynamic random access memory.
Claim 34
Dependent Claim
38 words
The memory device of claim 22 wherein the memory device comprises more than two bank memory arrays, and wherein the second bank memory array is predefined as a closest bank memory array to the first bank memory array.
Claim 35
Dependent Claim
46 words
The memory device of claim 22 wherein the memory device comprises more than two bank memory arrays, and wherein the second bank memory array is the most recently accessed bank memory array prior to the initiation of the transfer command to the first bank memory array.
Claim 36
Independent Claim
172 words
A method of initiating commands in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, an active command controlling an active operation; performing the active operation which includes the steps of latching a value representing a row address of a first bank memory array and activating the addressed row of storage cells in the first bank memory array; initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation for transferring data to or from the first bank memory array; and automatically initiating, at the second active edge of the system clock, in response to the active command, a responsive to the active command a precharge command controlling a precharge operation; and performing the precharge operation which includes the steps of precharging and deactivating a second bank memory array.
Claim 37
Independent Claim
172 words
A method of initiating commands in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, an active command controlling an active operation; performing the active operation which includes the steps of latching a value representing a row address of a first bank memory array and activating the addressed row of storage cells in the first bank memory array; initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation for transferring data to or from the first bank memory array; and automatically initiating, at the second active edge of the system clock, in response to the active command, a responsive to the active command a precharge command controlling a precharge operation; and performing the precharge operation which includes the steps of precharging and deactivating a second bank memory array.
Claim 38
Dependent Claim
50 words
The method of claim 33 further comprising the steps of: initiating, at a second active edge of the system clock, in response to selected command signals, a transfer command controlling a transfer operation; and performing the transfer operation which includes transferring data to or from the first bank memory array.
Claim 39
Dependent Claim
119 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a first bank memory array having storage cells organized in rows and columns for storing data; a second bank memory array having storage cells organized in rows and columns for storing data; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a special transfer command controlling a transfer operation for transferring data to or from the first bank memory array, and to automatically initiate at the first active edge of the system clock, a second command controlling a second operation on the second bank memory array.
Claim 40
Dependent Claim
119 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a first bank memory array having storage cells organized in rows and columns for storing data; a second bank memory array having storage cells organized in rows and columns for storing data; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a special transfer command controlling a transfer operation for transferring data to or from the first bank memory array, and to automatically initiate at the first active edge of the system clock, a second command controlling a second operation on the second bank memory array.
Claim 41
Dependent Claim
28 words
The memory device of claim 35 wherein the second command is a precharge command and wherein the second operation includes precharging and deactivating the second bank memory array.
Claim 42
Dependent Claim
30 words
The memory device of claim 35 wherein the transfer command is a read command and the transfer operation reads data from a storage cell in the first bank memory array.
Claim 43
Dependent Claim
30 words
The memory device of claim 35 wherein the transfer command is a write command and the transfer operation writes dam to a storage cell in the first bank memory array.
Claim 44
Independent Claim
98 words
A method of initiating commands in a synchronous memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a special transfer command controlling a transfer operation for transferring data to or from a first bank memory array; and automatically initiating, at the first active edge of the system clock, in response to the selected command signals, a second command controlling a second operation on a second bank memory array.
Claim 45
Independent Claim
98 words
A method of initiating commands in a synchronous memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a special transfer command controlling a transfer operation for transferring data to or from a first bank memory array; and automatically initiating, at the first active edge of the system clock, in response to the selected command signals, a second command controlling a second operation on a second bank memory array.
Claim 46
Dependent Claim
30 words
The method of claim 39 wherein the second command is a precharge command and wherein the second operation includes the steps of precharging and deactivating the second bank memory array.
Claim 47
Dependent Claim
35 words
The method of claim 39 wherein the special transfer command is a Special read command and the transfer operation includes the step of reading data from a storage cell in the first bank memory array.
Claim 48
Dependent Claim
35 words
The method of claim 39 wherein the special transfer command is a special write command and the transfer operation includes the step of writing data to a storage cell in the first bank memory array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |