Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs

Claim 2

A memory bank having a plurality of random access memories, comprising: a) an internal refresh circuit for each of said random access memories, each said internal refresh circuit, when actuated, providing memory preservation to at least one of said random access memories; b) a bi-directional external refresh pin for each of said random access memories, each of said bi-directional external refresh pins capable of receiving a refresh message and said refresh message generated by one of said random access memories; c) a common node in electrical communication with each of said bi-directional external refresh pins; and d) said random access memories interacting one with the other through said common node such that when one of said random access memories generates said refresh message all of said plurality of random access memories are refreshed in response to said refresh message.

Claim 3

The memory bank as specified in claim 1, wherein said refresh message is communicated from said bi-directional external refresh pin of said random access memory having said activated refresh circuit to said bi-directional external refresh pins of remaining said random access memories of said bank.

Claim 4

The memory bank as specified in claim 1, wherein the said bi-directional external refresh pins are electrically connected in a wired AND configuration at said common node.

Claim 5

The memory bank as specified in claim 1, further comprising a resistive element electrically interposed between said common node and a supply potential such that said bi-directional external refresh pins are capable of being passively pulled to said supply potential through said resistive element.

Claim 6

The memory bank as specified in claim 1, further comprising a resistive element for each refresh circuit, each of said resistive elements electrically interposed between one of said bi-directional refresh pins and a supply potential, such that said bi-directional external refresh pins are capable of being passively pulled to said supply potential through their respective said resistive elements.

Claim 7

The memory bank as specified in claim 5, wherein said bi-directional refresh pins are passively pulled to said supply potential when said internal refresh circuits are deactuated.

Claim 8

The memory bank as specified in claim 1, wherein said bank is a portion of a computer system having a microprocessor, and wherein said refresh message on said common node signals said microprocessor to wait.

Claim 9

The memory bank as specified in claim 1, wherein said internal refresh circuits of each of said random access memories are substantially synchronously activated.

Claim 10

The memory bank as specified in claim 1, wherein said random access memories are dynamic random access memories.

Claim 11

The memory bank as specified in claim 1, wherein said random access memories are static random access memories.

Claim 12

The memory bank as specified in claim 10, wherein said static random access memories are pseudo static random access memories characterized as having said internal refresh circuit and non-multiplex addressing.

Claim 13

The memory bank as specified in claim 1, further comprising a control device for each random access device of said bank, said control device interposed between said bi-directional external refresh pin and a reference node, said reference node connectable to a reference potential, wherein said control device is activated at a termination of a timing sequence, said activation pulling said bi-directional refresh pin to a same potential as said reference node thereby generating said refresh message.

Claim 14

The memory bank as specified in claim 12, wherein said control device is a transistor.

Claim 15

The memory bank as specified in claim 1, further comprising a timing circuit for each of said random access memories, each of said timing circuits determining a refresh cycle, said refresh cycle having a timing sequence for a periodic refresh rate.

Claim 16

The memory bank as specified in claim 14, wherein during said timing sequence said timing circuit specifies when a row is to refresh and increments a row address for a subsequent refresh.

Claim 17

The memory bank as specified in claim 14, further comprising an arbitration circuit for each of said random access memories, an output of said timing circuit routed to said arbitration circuit, said arbitration circuits capable of enabling and disabling said refresh circuits and capable of generating said refresh message in response to said output of said timing circuit.

Claim 18

The memory bank as specified in claim 16, wherein said arbitration circuit is capable of receiving said refresh message.

Claim 19

The memory bank as specified in claim 14, further comprising a master random access memory, said master random access memory being one of said plurality of random access memories, said master random access memory meeting a refresh activation timing specification, said internal refresh circuit of said master activated in response to meeting said timing specification and the bi-directional external refresh pin of said master communicating said refresh message to remaining said random access memories of said bank through remaining said bi-directional external refresh pins, such that said internal refresh circuits of remaining said random access memories are activated, thereby providing substantially synchronous refreshing of said plurality of random access memories.

Claim 20

The memory bank as specified in claim 18, wherein said timing circuits of remaining said random access memories are deactivated in response to said refresh message, said timing circuit of said master thereby controlling said timing sequence of said plurality of random access memories.

Claim 21

The memory bank as specified in claim 18, wherein said timing specification requires said master to have a fastest timing sequence of said bank.

Claim 22

The memory bank as specified in claim 18, wherein a reset pulse synchronizes each of said timing circuits of said bank to a same state thereby substantially initiating concurrent activation of all of said timing circuits.

Claim 23

The memory bank as specified in claim 18, wherein a memory operation of said memory bank is only interrupted once per row refresh.

Claim 24

The memory bank as specified in claim 18, wherein said master random access memory continues to periodically generate said refresh message thereby effecting said refresh cycle in said plurality of random access memories.

Claim 25

The memory bank as specified in claim 18, wherein said memory preservation is provided only by said internal refresh circuit of said master random access memory, said timing circuits and said internal refresh circuits remaining said random access memories disabled.

Claim 26

The memory bank as specified in claim 14, wherein a reset pulse synchronizes each of said timing circuits of said bank to same state thereby substantially initiating concurrent activation of all of said timing circuits.

Claim 27

A random access memory, comprising: a) an internal refresh circuit, when actuated, capable of providing memory preservation to said random access memory; b) a bi-directional external refresh pin connectable to a common node, said bi-directional external refresh pin capable of receiving a refresh message and communicating said refresh message from and to said common node respectively; c) a timing circuit for determining a refresh cycle, said refresh cycle having a timing sequence for a periodic refresh rate; d) an arbitration circuit capable of enabling and disabling said internal refresh circuit and capable of generating said refresh message in response to a signal from said timing circuit and capable of receiving said refresh message; and e) said random access memory capable of interacting with at least one other random access memory, said random access memories communicating through said common node such that when one of said internal refresh circuits of one of said random access memories is activated said random access memory in electrical communication with said common node is refreshed in response to said refresh message.

Claim 28

A random access memory, comprising: a) an internal refresh circuit, when actuated, capable of providing memory preservation to said random access memory; b) a bi-directional external refresh pin connectable to a common node, said bi-directional external refresh pin capable of receiving a refresh message and communicating said refresh message from and to said common node respectively; c) a timing circuit for determining a refresh cycle, said refresh cycle having a timing sequence for a periodic refresh rate; d) an arbitration circuit capable of enabling and disabling said internal refresh circuit and capable of generating said refresh message in response to a signal from said timing circuit and capable of receiving said refresh message; and e) said random access memory capable of interacting with at least one other random access memory, said random access memories communicating through said common node such that when one of said internal refresh circuits of one of said random access memories is activated said random access memory in electrical communication with said common node is refreshed in response to said refresh message.

Claim 29

The random access memory as specified in claim 26, wherein said random access memory is a master random access memory when said random access memory meets a refresh activation timing specification, in response to meeting said timing specification said internal refresh circuit of said master is activated and said master generates said refresh message at its respective said bidirectional external refresh pin, said master thereby controlling said timing sequence of said random access memory in electrical communication with said common node to substantially synchronize a refresh cycle of said random access memory in electrical communication with said common node.

Claim 30

The random access memory as specified in claim 27, wherein said timing circuit of said random access memory is deactivated when in electrical communication with said master random access memory having generated said refresh message.

Claim 31

The random access memory as specified in claim 27, wherein said master random access memory continues to periodically generate said refresh message, said refresh message capable of synchronously effecting a refresh cycle in a plurality of said random access memories.

Claim 32

The random access memory as specified in claim 27, wherein said memory preservation of said random access memory in electrical communication with said common node is provided only by said internal refresh circuit of said master random access memory, said timing circuit and said internal refresh circuit of said random access memory other than said master being disabled.

Claim 33

The random access memory as specified in claim 26, further comprising a resistive element electrically interposed between said bi-directional refresh pin and a supply potential, such that said bi-directional external refresh pin is capable of being passively pulled to said supply potential through said resistive element.

Claim 34

The random access memory as specified in claim 26, wherein said bi-directional refresh pin is passively pulled to said a supply potential when no refresh message is generated.

Claim 35

The random access memory as specified in claim 26, wherein said common node is in electrical communication with a microprocessor of a computer system such that when said refresh message is asserted at said bi-directional external refresh pin, said refresh message signals said microprocessor to wait.

Claim 36

The random access memory as specified in claim 26, wherein said random access memory is a dynamic random access memory.

Claim 37

The random access memory as specified in claim 26, wherein said random access memory is a static random access memory.

Claim 38

The random access memory as specified in claim 35, wherein said static random access memory is a pseudo static random access memory characterized as having said internal refresh circuit and non-multiplex addressing.

Claim 39

The random access memory as specified in claim 26, wherein said arbitration circuit comprises a control device, said control device interposed between said bi-directional external refresh pin and a reference node, said reference node connectable to a reference potential, wherein said control device is activated at a termination of said timing sequence, said activation pulling said bi-directional refresh pin to a same potential as said reference node thereby generating said refresh message.

Claim 40

The random access memory as specified in claim 37, wherein said control device is a transistor.

Claim 41

The random access memory as specified in claim 26, wherein: a) said timing circuit further comprises a timing circuit input terminal and a timing circuit output terminal, said timing circuit capable of generating inactive and active output signals at said timing circuit output terminal; and wherein b) said arbitration circuit further comprise a control device and a control circuit, said control device interposed between said bi-directional external refresh pin and a reference node, said reference node connectable to said reference potential, said control circuit having a first control circuit input terminal for receiving said refresh message from said bi-directional external refresh pin and a second control circuit input terminal for receiving said inactive and active output signals from said timing circuit output terminal, said control circuit having a first control circuit output terminal, a second control circuit output terminal and a third output terminal, said first control circuit output terminal capable of providing a refresh signal to said internal refresh circuit in order to initiate said refresh cycle in response to said refresh message and in response to said timing output signal of said timing circuit, said second control circuit output terminal providing a pulse to said timing circuit input terminal to initiate said timing sequence, and said third output terminal providing a signal at an input terminal of said control device for activating and deactivating said control device wherein said activating of said control device routes said reference potential from said reference node to said bi-directional external refresh pin through said control device thereby generating said refresh message, and wherein said deactivating of said control device allows said bi-directional external refresh pin to be passively pulled to a supply potential and to be pulled to a potential of said common node.

Claim 42

The random access memory as specified in claim 26, wherein during said timing sequence said timing circuit specifies when a row is to refresh and increments a row address for a subsequent refresh.