Processor controlled memory refresh

Claim 2

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve the stored information, each said dynamic memory unit having refresh means incorporated therein for performing said required periodic refreshing; an electrical connection between said processor and said memory system; detecting means responsive to at least a portion of an instruction within said processor for detecting when a non-memory operation is taking place; said electrical connection between said processor and said memory system being responsive to said detecting means and including means for transmitting a signal to each of said memory units, when said processor is performing a non-memory operation; and means responsive to said refresh means incorporated in each said dynamic memory unit for determining that a refresh was accomplished thereby setting a new time reference before a next subsequent refresh of the stored information is required.

Claim 3

A data processing system as in claim 1 wherein said means for detecting when a non-memory operation is taking place is contained within said processor.

Claim 4

Apparatus as in claim 1 wherein said means for determining that a refresh was accomplished is contained within each said plurality of dynamic memory units.

Claim 5

Apparatus as in claim 1 further comprising: a read only storage unit for controlling said processor to perform instructions in a serial mode.

Claim 6

Apparatus as in claim 4 wherein said means for detecting when a non-memory operation is taking place comprises: a force regeneration circuit which receives an extra bit position signal from said read only storage unit via said processor indicating when a non-memory operation is taking place, said force regeneration circuit also receiving a clock signal for providing a force refresh signal to each of said memory units.

Claim 7

Apparatus as in claim 1 wherein said means for detecting when a non-memory operation is taking place comprises: a force regenerating circuit responsive to a portion of an instruction within said processor, said force regenerating circuit also being responsive to a clock signal; and means within said force regenerating circuit for determining when a non-memory operation is taking place; whereby said force regenerating circuit provides a refresh signal to said means for transmitting upon the occurrence of said clock signal.

Claim 8

Apparatus as in claim 1 wherein said means for detecting when a non-memory operation is taking place comprises: a regeneration circuit which receives an instruction bit from said processor indicating that said memory system is not required, said regeneration circuit also receiving a clock signal and providing a force refresh signal to each of said memory units.

Claim 9

Apparatus as in claim 1 wherein said processor is a first processor, said data processing system additionally comprising: a second processor having defined time intervals during which either memory, or non-memory operations take place; an electrical connection between said first processor and said second processor; an electrical connection between said memory system and both said first and said second processor said last mentioned connection between said first processor and said memory system including means for transmitting a force refresh signal to said memory system, when both said first and second processor are performing a non-memory operation, said first processor being a maintenance processor controlling when said memory system is force refreshed.

Claim 10

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; and means for detecting when a non-memory operation is taking place and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place; said means for detecting being connected to said processor and comprising: a force regenerating circuit responsive to a portion of an instruction within said processor, said force regenerating circuit also being responsive to a clock signal; and means within said force regenerating circuit for determining when a memory idle operation is taking place; whereby said force generating circuit provides a refresh signal upon the occurrance of said clock input signal.

Claim 11

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; and means for detecting when a non-memory operation is taking place and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place; said means for detecting being connected to said processor and comprising: a force regenerating circuit responsive to a portion of an instruction within said processor, said force regenerating circuit also being responsive to a clock signal; and means within said force regenerating circuit for determining when a memory idle operation is taking place; whereby said force generating circuit provides a refresh signal upon the occurrance of said clock input signal.

Claim 12

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; and means for detecting when a non-memory operation is taking place and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place; said means for detecting being connected to said processor and comprising: a regeneration circuit which receives an instruction bit from said processor indicating that said memory system is not required, said regeneration circuit also receiving a clock signal and providing a force refresh signal to each of said memory units.

Claim 13

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; and means for detecting when a non-memory operation is taking place and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place; said means for detecting being connected to said processor and comprising: a regeneration circuit which receives an instruction bit from said processor indicating that said memory system is not required, said regeneration circuit also receiving a clock signal and providing a force refresh signal to each of said memory units.

Claim 14

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; means for detecting when a non-memory operation is taking place, and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place; and a read only storage unit for controlling said processor to perform instructions in a serial mode; said means for detecting being connected to said processor and comprising: a force regeneration circuit which receives an extra bit position signal from said read only storage unit via said processor indicating when a non-memory operation is taking place, said force regeneration circuit also receiving a clock signal for providing a force refresh to each of said memory units.

Claim 15

A data processing system having a processor for processing electronic digital information, said processor having defined time intervals during which either memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; means for detecting when a non-memory operation is taking place, and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place; and a read only storage unit for controlling said processor to perform instructions in a serial mode; said means for detecting being connected to said processor and comprising: a force regeneration circuit which receives an extra bit position signal from said read only storage unit via said processor indicating when a non-memory operation is taking place, said force regeneration circuit also receiving a clock signal for providing a force refresh to each of said memory units.

Claim 16

A data processing system having a first processor for processing electronic digital information, said first processor having defined time intervals during which with memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; means for detecting when a non-memory operation is taking place and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place, said means for detecting being connected to said first processor; a second processor having defined time intervals during which either memory, or non-memory operations take place; an electrical connection between said first processor and said second processor; and an electrical connection between said memory system and both said first and said second processor said last mentioned electrical connection between said first processor and said memory system including means for transmitting a force refresh signal to said memory system when both said first and said second processors are performing a non-memory operation, said first processor being a maintenance processor controlling when said memory system is force refreshed.

Claim 17

A data processing system having a first processor for processing electronic digital information, said first processor having defined time intervals during which with memory, or non-memory operations take place, the improvement comprising: a memory system including a plurality of dynamic memory units each of said memory units requiring a refresh signal to preserve stored information; means for detecting when a non-memory operation is taking place and for causing said memory system to be refreshed during the time interval when said non-memory operation is taking place, said means for detecting being connected to said first processor; a second processor having defined time intervals during which either memory, or non-memory operations take place; an electrical connection between said first processor and said second processor; and an electrical connection between said memory system and both said first and said second processor said last mentioned electrical connection between said first processor and said memory system including means for transmitting a force refresh signal to said memory system when both said first and said second processors are performing a non-memory operation, said first processor being a maintenance processor controlling when said memory system is force refreshed.