US3748651A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Refresh control for add-on semiconductor memory
Assignee: Cogar Corp
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Filing: 1972-02-16
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Granted: 1973-07-24
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Expires: 1992-02-16
Abstract
Abstract A circuit for controlling refresh operations of a dynamic MOS add-on memory. The need for a refresh operation is determined by a 4.5-microsecond clock. If the memory has not been selected in the recent past, in response to the clock signal a separate refresh cycle is initiated. If a read or write cycle is in progress when the clock signal is generated, a separate refresh cycle is executed a predetermined time after the termination of the read or write cycle. If a separate refresh operation is interrupted by a command to execute a read or write cycle, then the memory is operated in a mode in which it is automatically refreshed at the end of the read or write cycle.
Inventors
- 👤 R Mesnik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
225 words
A circuit for controlling refresh operations of a dynamic MOS add-on memory used in conjunction with a data processor, said add-on memory being operative in an automatic mode in which the memory is refreshed automatically at the end of a read or write cycle and being further operative in a separate refresh mode in which the memory is refreshed during a separate refresh cycle without a read or write operation being performed during the cycle, comprising clock means for generating periodic clock pulses indicative of a need for the memory to be refreshed, means responsive to the memory not having executed a read or write cycle for a predetermined time interval when a clock is pulse is generated for controlling the immediate execution of a separate refresh cycle, means responsive to the memory either executing a read or write cycle or having terminated the execution of such a cycle within said predetermined time interval when a clock pulse is generated for controlling the execution of a separate refresh cycle upon the termination of said predetermined time interval following the last read or write cycle, and means responsive to a command from said data processor to execute a read or write operation for interrupting a separate refresh cycle if such a cycle is in progress and for controlling said memory to operate in said automatic mode.
Claim 2
Dependent Claim
225 words
A circuit for controlling refresh operations of a dynamic MOS add-on memory used in conjunction with a data processor, said add-on memory being operative in an automatic mode in which the memory is refreshed automatically at the end of a read or write cycle and being further operative in a separate refresh mode in which the memory is refreshed during a separate refresh cycle without a read or write operation being performed during the cycle, comprising clock means for generating periodic clock pulses indicative of a need for the memory to be refreshed, means responsive to the memory not having executed a read or write cycle for a predetermined time interval when a clock is pulse is generated for controlling the immediate execution of a separate refresh cycle, means responsive to the memory either executing a read or write cycle or having terminated the execution of such a cycle within said predetermined time interval when a clock pulse is generated for controlling the execution of a separate refresh cycle upon the termination of said predetermined time interval following the last read or write cycle, and means responsive to a command from said data processor to execute a read or write operation for interrupting a separate refresh cycle if such a cycle is in progress and for controlling said memory to operate in said automatic mode.
Claim 3
Dependent Claim
101 words
A circuit for controlling refresh operations of a dynamic MOS add-on memory used in conjunction with a data processor in accordance with claim 1 further including means for generating timing signals, bistable means for defining one of a pluarlity of system states, means for switching said bistable means from defining one system state to define another system state in accordance with respective generated timing signals and signals received from said data processor while said bistable means define said one system state, and means for controlling refresh operations in accordance with generated timing signals while said bistable means define respective system states.
Claim 4
Dependent Claim
48 words
A circuit for controlling refresh operations of a dynamic MOS add-on memory used in conjunction with a data processor in accordance with claim 2 wherein said clock pulses are generated at intervals short enough to ensure the refreshing of said memory at intervals shorter than a predetermined value.
Claim 5
Dependent Claim
66 words
A circuit for controlling refresh operations of a dynamic MOS add-on memory used in conjunction with a data processor in accordance with claim 2 wherein said data processor initiates a read or write operation with the generation of a system select pulse, and refresh operations are controlled to occur at times determined only by the times of occurrence of system select pulses and generated clock pulses.
Claim 6
Dependent Claim
66 words
A circuit for controlling refresh operations of a dynamic MOS add-on memory used in conjunction with a data processor in accordance with claim 1 wherein said data processor initiates a read or write operation with the generation of a system select pulse, and refresh operations are controlled to occur at times determined only by the times of occurrence of system select pulses and generated clock pulses.
Claim 7
Dependent Claim
156 words
A circuit for controlling refresh operations of a dynamic MOS memory used as an add-on memory for a data processor, said memory being operative in a first mode in which it is refreshed at the end of a read or write cycle and being further operative in a second mode in which it is refreshed during a separate refresh cycle without a read or write operation being performed during the cycle, comprising means for generating a pulse indicative of a need for the memory to be refreshed, means responsive to the generation of a pulse for operating the memory in said second mode in accordance with the time when a previous read or write operation was performed, and means responsive to a command from said data processor to execute a read or write operation for interrupting the operation of the memory in said second mode and for controlling the memory to operate in said first mode.
Claim 8
Dependent Claim
156 words
A circuit for controlling refresh operations of a dynamic MOS memory used as an add-on memory for a data processor, said memory being operative in a first mode in which it is refreshed at the end of a read or write cycle and being further operative in a second mode in which it is refreshed during a separate refresh cycle without a read or write operation being performed during the cycle, comprising means for generating a pulse indicative of a need for the memory to be refreshed, means responsive to the generation of a pulse for operating the memory in said second mode in accordance with the time when a previous read or write operation was performed, and means responsive to a command from said data processor to execute a read or write operation for interrupting the operation of the memory in said second mode and for controlling the memory to operate in said first mode.
Claim 9
Dependent Claim
102 words
A circuit for controlling refresh operations of a dynamic MOS memory used as an add-on memory for a data processor in accordance with claim 6 further including means for generating timing signals, bistable means for defining one of a plurality of system states, means for switching said bistable means from defining one system state to define another system state in accordance with respective generated timing signals and signals received from said data processor while said bistable means define said one system state, and means for controlling refresh operations in accordance with generated timing signals while said bistable means define respective system states.
Claim 10
Dependent Claim
48 words
A circuit for controlling refresh operations of a dynamic MOS memory used as an add-on memory for a data processor in accordance with claim 7 wherein said pulses are generated at intervals short enough to ensure the refreshing of said memory at intervals shorter than a predetermined value.
Claim 11
Dependent Claim
67 words
A circuit for controlling refresh operations of a dynamic MOS memory used as an add-on memory for a data processor in accordance with claim 7 wherein said data processor initiates a read or write operation with the generation of a system select pulse, and refresh operations are controlled to occur at times determined only by the times of occurrence of system select pulses and said generated pulses.
Claim 12
Dependent Claim
67 words
A circuit for controlling refresh operations of a dynamic MOS memory used as an add-on memory for a data processor in accordance with claim 6 wherein said data processor initiates a read or write operation with the generation of a system select pulse, and refresh operations are controlled to occur at times determined only by the times of occurrence of system select pulses and said generated pulses.
References Cited (Backward Citations)
US3541530A
Cited
US3576571A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-23 | 1977-01-22 | 1977-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-23 | 1981-01-22 | 1981-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-23 | 1985-01-22 | 1985-07-24 | $7700.00 | Window Closed / Lapsed |