Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system

Claim 2

Method of operating a module of memory circuits with at least two data processors which may be selectively gated thereto through separate signal ports of the module, said memory circuits requiring periodic refreshing of stored logic manifestations in accordance with a sequence of refresh clock signals applied thereto, the method comprising the steps of: providing sequences of refresh clock signals for each signal port of the module; selectively gating a sequence of refresh clock signals present at one signal port of the module to the memory circuits for producing a refresh operation thereof; and preserving an indication of the occurrences of the refresh operations performed on the memory circuits of the module independently of the signal port thereof through which the sequence of refresh clock signals for each such refresh operation is selectively gated for preserving an indication of the status of memory refresh operations as the signal ports are selectively gated.

Claim 3

Method of operating a module of memory circuits as in claim 1 wherein the step of selectively gating includes applying to the memory circuits of the module the sequence of refresh clock signals present at the one signal port through which one of said separate data processors is gated to the memory circuits of the module at the time of a required refresh operation.

Claim 4

Method of operating a module of memory circuits as in claim 1 wherein the step of selectively gating includes applying to the memory circuits of the module the sequence of refresh clock signals present at the one signal port through which the one of said separate data processors was last gated to the memory circuits of the module prior to the time of a required refresh operation.

Claim 5

Method of operating a module of memory circuits as in claim 1 wherein the step of selectively gating includes applying to the memory circuits of the module the sequence of refresh clock signals present at a predetermined one of the signal ports of the module under conditions of no data processor being gated to the memory circuits of the module at the time of a required refresh operation.

Claim 6

Method of operating a module of memory circuits as in claim 1 in which operation of data processors with the memory circuits is performed within an operating interval that is shorter than the periodicity of the required refresh operations, and the method comprises: detecting the presence of any pending priority requirements for access to the memory circuits of the module by a data processor at the time of a required refresh operation; deferring the application of the sequence of refresh clock signals to the memory circuits and selectively gating such data processors to the memory circuits of the module during the next succeeding operating interval following the required refresh operation; and applying a sequence of refresh clock signals to the memory means of the module in the succeeding operating interval which next follows selectively gating the data processor to the memory circuits.

Claim 7

Modular memory apparatus comprising: a circuit module having a pair of signal ports and including memory circuits for operation with at least two separate memory-using data processors that may be selectively gated thereto through the pair of signal ports of the module, and which require periodic refreshing of stored logic manifestations in accordance with a sequence of refresh clock signals applied thereto; a circuit module controller means connecting a memory-using data processor to a corresponding one of the signal ports of the circuit module, each of said circuit module controller means including timing means for recurringly applying to the corresponding signal port the sequence of refresh clock signals required for said refresh operations; said circuit module includes gating means connected to said memory circuits for selective connection thereof to one of the pair of signal ports for operatively coupling the corresponding data processor thereto; said circuit module also includes accumulator means connected to the memory circuits for preserving an indication of the status of the refreshing thereof; and detector means coupled to the accumulator means of the circuit module for causing the accumulator means to preserve an indication of the status of the refreshing operation of the memory circuits of such circuit module, independently of which of the signal ports is gated to the memory circuits in response to the detection of a refresh operation.

Claim 8

Modular memory apparatus comprising: a circuit module having a pair of signal ports and including memory circuits for operation with at least two separate memory-using data processors that may be selectively gated thereto through the pair of signal ports of the module, and which require periodic refreshing of stored logic manifestations in accordance with a sequence of refresh clock signals applied thereto; a circuit module controller means connecting a memory-using data processor to a corresponding one of the signal ports of the circuit module, each of said circuit module controller means including timing means for recurringly applying to the corresponding signal port the sequence of refresh clock signals required for said refresh operations; said circuit module includes gating means connected to said memory circuits for selective connection thereof to one of the pair of signal ports for operatively coupling the corresponding data processor thereto; said circuit module also includes accumulator means connected to the memory circuits for preserving an indication of the status of the refreshing thereof; and detector means coupled to the accumulator means of the circuit module for causing the accumulator means to preserve an indication of the status of the refreshing operation of the memory circuits of such circuit module, independently of which of the signal ports is gated to the memory circuits in response to the detection of a refresh operation.

Claim 9

Modular memory apparatus as in claim 6 wherein said gating means of the circuit module includes means coupled to the memory circuits for providing the sequence of refresh clock signals present at the one signal port of the circuit module through which a memory-using data processor is coupled to the memory circuits at the time for a required refresh operation of the memory circuits.

Claim 10

Modular memory apparatus as in claim 6 wherein said gating means of the circuit module includes means coupled to the memory circuits for providing the sequence of refresh clock signals present at the one signal port of the circuit module through which a memory-using data processor was last gated to the memory circuits of the circuit module prior to the time of a required refresh operation of the memory circuits.

Claim 11

Modular memory apparatus as in claim 6 wherein said gating means of the circuit module includes means coupled to the memory circuits for providing the sequence of refresh clock signals present at a preselected one of the signal ports of the circuit module for a required refresh operation of said memory circuits in response to the condition that neither signal port is gated to the memory circuits at the time of the required refresh operation.