Apparatus and method for memory refreshment control

Claim 2

In a memory module associated with a data processing unit wherein information in groups of memory elements is to be refreshed by a refresh means, apparatus for controlling the refreshing of said groups of memory elements comprising: a first control unit enabled during a first period to control said refresh means to refresh said information in said memory elements during an interval of said first period when said data processing unit does not require access to said memory elements; and a second control unit, enabled during a second period following said first period by a failure of said refresh means to refresh said information in said memory elements during said first period, to control said refresh means to refresh said information in said memory elements during an interval of said second period.

Claim 3

In a memory module associated with a data processing unit, apparatus comprising: memory elements for storing binary signals; controllable refresh means coupled to said memory elements for refreshing said binary signals in a selected group of said memory elements in response to a control signal; control means, coupled to said memory elements and to said refresh means, for establishing said selected group addressed by said refresh means and for issuing said control signal, wherein said control signal is issued during an interval of a first period when said data processing unit does not require access to said selected group, wherein a non-issuance of said control signal during said first period causes said control signal to be issued during a second period following said first period, and wherein said refresh means addresses a different selected group after issuance of said control signal; and disabling means coupled to said control means, for preventing an issuance of said control signal for a remaining portion of said first period and said second period after access to said selected group by said data processing unit.

Claim 4

In a memory module associated with a data processing unit, apparatus comprising: memory elements for storing binary signals; controllable refresh means coupled to said memory elements for refreshing said binary signals in a selected group of said memory elements in response to a control signal; control means, coupled to said memory elements and to said refresh means, for establishing said selected group addressed by said refresh means and for issuing said control signal, wherein said control signal is issued during an interval of a first period when said data processing unit does not require access to said selected group, wherein a non-issuance of said control signal during said first period causes said control signal to be issued during a second period following said first period, and wherein said refresh means addresses a different selected group after issuance of said control signal; and disabling means coupled to said control means, for preventing an issuance of said control signal for a remaining portion of said first period and said second period after access to said selected group by said data processing unit.

Claim 5

In a memory module associated with a data processing unit, the combination comprising: memory elements for storing binary information; controllable refresh means coupled to said memory element for refreshing said binary information in a selected group of said memory elements in response to an activation signal; controllable address means coupled to said memory elements for determining said selected group of said memory elements in response to an address signal, wherein said address signal causes said address means to determine a different selected group of said memory elements; signal means coupled to said refresh means and said address means for producing said activation signal and said address signal, during each of a series of intervals, said activation signal produced during a period of non-access of said memory module by said data processing unit in a first subinterval of each of said intervals, said activation signal produced during a second subinterval of each of said intervals when said period of non-access does not occur in said first subinterval; clock means coupled to said signal means for establishing said intervals and for establishing said first subinterval and said second subinterval thereof; and apparatus for disabling said signal means from producing said activation signal during a portion of said interval remaining after said selected group is accessed by said data processing unit.

Claim 6

In a memory module associated with a data processing unit, the combination comprising: memory elements for storing binary information; controllable refresh means coupled to said memory element for refreshing said binary information in a selected group of said memory elements in response to an activation signal; controllable address means coupled to said memory elements for determining said selected group of said memory elements in response to an address signal, wherein said address signal causes said address means to determine a different selected group of said memory elements; signal means coupled to said refresh means and said address means for producing said activation signal and said address signal, during each of a series of intervals, said activation signal produced during a period of non-access of said memory module by said data processing unit in a first subinterval of each of said intervals, said activation signal produced during a second subinterval of each of said intervals when said period of non-access does not occur in said first subinterval; clock means coupled to said signal means for establishing said intervals and for establishing said first subinterval and said second subinterval thereof; and apparatus for disabling said signal means from producing said activation signal during a portion of said interval remaining after said selected group is accessed by said data processing unit.

Claim 7

In a memory module associated with a data processing unit, a method for controlling activation of a refresh means for refreshing information in groups of memory elements, a one of said groups of memory elements selected by a memory control circuit, to be refreshed during an interval, comprising: dividing said interval into a first and a second subinterval, said refresh means activated by a single activation signal during said interval; generating said single activation signal during a period of non-activity of said memory module occurring during said first subinterval; generating said single activation signal during said second subinterval at a conclusion of an access of said memory module occurring at a beginning of said second subinterval when said period of non-activity of said memory module does not occur during said first subinterval; delivering a signal to said memory control circuit for selection of a new one of said groups of memory elements during a next interval; and disabling said refresh means for a remainder of said interval after said one of said groups of memory elements is accessed by said data processing unit.

Claim 8

In a memory module associated with a data processing unit, a method for controlling activation of a refresh means for refreshing information in groups of memory elements, a one of said groups of memory elements selected by a memory control circuit, to be refreshed during an interval, comprising: dividing said interval into a first and a second subinterval, said refresh means activated by a single activation signal during said interval; generating said single activation signal during a period of non-activity of said memory module occurring during said first subinterval; generating said single activation signal during said second subinterval at a conclusion of an access of said memory module occurring at a beginning of said second subinterval when said period of non-activity of said memory module does not occur during said first subinterval; delivering a signal to said memory control circuit for selection of a new one of said groups of memory elements during a next interval; and disabling said refresh means for a remainder of said interval after said one of said groups of memory elements is accessed by said data processing unit.

Claim 9

A process for initiating a restoration of physical states of groups of volatile memory elements of a memory module, comprising the steps of: initiating said restoration of an addressed one of said groups during a free period of said memory module, said free period occurring during a first part of an interval allotted for said restoration; initiating said restoration of said addressed group during a second part of said interval when said free period is unavailable during said first part; addressing a new one of said groups of memory elements; and repeating above steps so that said physical states of all of said memory elements are restored while said physical states can be determined.

Claim 10

A process for initiating a restoration of physical states of groups of volatile memory elements of a memory module, comprising the steps of: initiating said restoration of an addressed one of said groups during a free period of said memory module, said free period occurring during a first part of an interval allotted for said restoration; initiating said restoration of said addressed group during a second part of said interval when said free period is unavailable during said first part; addressing a new one of said groups of memory elements; and repeating above steps so that said physical states of all of said memory elements are restored while said physical states can be determined.

Claim 11

In a memory module associated with a data processing unit wherein information in groups of memory elements is to be refreshed by a refresh means, apparatus for controlling a refreshing of said groups of memory elements comprising: first control unit means coupled to said refresh means controlling said refreshing of said information in said groups of memory elements during a period of non-use of said groups; second control unit means controlling said refreshing of said information in said groups of memory elements after a predetermined interval of continuous use of said groups, wherein periods for refreshing said groups of memory elements are divided in said predetermined interval and a second interval; selection means to establish which one of said groups is to be refreshed; and clock means to determine said predetermined interval and said second interval, an enabling of said refresh means taking place during a total interval comprising said predetermined interval and said second interval.

Claim 12

In a memory module associated with a data processing unit wherein information in groups of memory elements is to be refreshed by a refresh means, apparatus for controlling a refreshing of said groups of memory elements comprising: first control unit means coupled to said refresh means controlling said refreshing of said information in said groups of memory elements during a period of non-use of said groups; second control unit means controlling said refreshing of said information in said groups of memory elements after a predetermined interval of continuous use of said groups, wherein periods for refreshing said groups of memory elements are divided in said predetermined interval and a second interval; selection means to establish which one of said groups is to be refreshed; and clock means to determine said predetermined interval and said second interval, an enabling of said refresh means taking place during a total interval comprising said predetermined interval and said second interval.

Claim 13

Apparatus recited in claim 6, wherein said memory elements are metal-oxide-semiconductor units.

Claim 14

In a memory module associated with a data processing unit wherein inFormation in groups of memory elements is to be refreshed by a refresh means, apparatus for controlling a refreshing of said groups of memory elements comprising: first control unit means coupled to said refresh means controlling said refreshing of said information in said groups of memory elements during a period of non-use of said groups; second control unit means controlling said refreshing of said information in said groups of memory elements after a predetermined period of continuous use of said groups; and means responsive to logic signals for activating said refresh means in a first part of an interval.

Claim 15

In a memory module associated with a data processing unit wherein inFormation in groups of memory elements is to be refreshed by a refresh means, apparatus for controlling a refreshing of said groups of memory elements comprising: first control unit means coupled to said refresh means controlling said refreshing of said information in said groups of memory elements during a period of non-use of said groups; second control unit means controlling said refreshing of said information in said groups of memory elements after a predetermined period of continuous use of said groups; and means responsive to logic signals for activating said refresh means in a first part of an interval.

Claim 16

Apparatus recited in claim 8 including means responsive to other logic signals for activating said refresh means in a second part of said interval.