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US3636528A
Expired / Lapsed
US
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Half-bit memory cell array with nondestructive readout
Assignee: Shell USA Inc
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Filing: 1969-11-14
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Granted: 1972-01-18
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Expires: 1989-11-14
Abstract
Abstract A half-bit memory array featuring nondestructive reading uses two X address circuits addressed at different times and coupled by an inverter to read the memory element in a first portion of the operational cycle, and refresh it in a second portion of the operational cycle, without disturbing the gate electrode potential of the memory element at any time during the cycle, and without the refresh signal level being dependent upon the read signal level. Writing is accomplished by disabling the inverter to prevent transfer of the read information to the refresh circuit and substituting in its place a low-impedance data input signal. Fast switching is accomplished by reducing charge transfer operations to a minimum, and the circuit is entirely ratioless to improve speed of operation and circuit size.
Inventors
- 👤 Dennis E Morris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
250 words
A ratioless random-access memory array comprising: a. a plurality of memory cells each including a memory element switchable between a conductive and a nonconductive state; b. a source of DC potential representing a first logic state; c. first bit line means; d. precharge means operative during a first portion of the operational cycle of said memory array for precharging said first bit line means to a precharge potential representing a second logic state; e. first thickness means in each of said cells responsive to a selected first address coordinate of the addressed cell and operative during a second portion of said operational cycle to connect said first bit line means to said DC potential source through said memory element so as to change the logic state of said first bit line if the said memory element is conductive; f. second bit line means; g. second address means in each of said cells responsive to said first address coordinate but operative during a third portion of said operational cycle to connect said memory element to said second bit line means so as to switch said memory element to the conductivity state determined by the logic state of said second bit line means; and h. inverter means interposed between said first and second bit line means to produce, during said third portion of said operational cycle, a logic state which is the inverse of the logic state existing in said first bit line means during said second portion of said operational cycle.
Claim 2
Dependent Claim
250 words
A ratioless random-access memory array comprising: a. a plurality of memory cells each including a memory element switchable between a conductive and a nonconductive state; b. a source of DC potential representing a first logic state; c. first bit line means; d. precharge means operative during a first portion of the operational cycle of said memory array for precharging said first bit line means to a precharge potential representing a second logic state; e. first thickness means in each of said cells responsive to a selected first address coordinate of the addressed cell and operative during a second portion of said operational cycle to connect said first bit line means to said DC potential source through said memory element so as to change the logic state of said first bit line if the said memory element is conductive; f. second bit line means; g. second address means in each of said cells responsive to said first address coordinate but operative during a third portion of said operational cycle to connect said memory element to said second bit line means so as to switch said memory element to the conductivity state determined by the logic state of said second bit line means; and h. inverter means interposed between said first and second bit line means to produce, during said third portion of said operational cycle, a logic state which is the inverse of the logic state existing in said first bit line means during said second portion of said operational cycle.
Claim 3
Dependent Claim
75 words
The array of claim 1, in which each of said cells has a second address coordinate, and which there is a plurality of first and second bit line means, any given first and second bit line means being common to all cells whose second address coordinate is the same; and second address means responsive to a selected second address coordinate for connecting a selected one of said bit line means to data output circuit means.
Claim 4
Dependent Claim
44 words
The array of claim 1, further comprising a source of write pulses, a source of input data, and means responsive to the appearance of write pulse to disable said inverter means and to connect said second bit line means to said input data source.
Claim 5
Dependent Claim
97 words
A random-access memory array, comprising: a. a plurality of individually addressable memory cells; b. first bit line means; c. means for establishing in said first bit line means a logic state opposite to the logic state of an addressed memory element; d. second bit line means; e. inverter means connected between said first and second bit line means to establish in said second bit line means a logic state equal to the logic state of said addressed memory element; and f. means for establishing in said memory element the logic state of said second bit line means.
Claim 6
Dependent Claim
97 words
A random-access memory array, comprising: a. a plurality of individually addressable memory cells; b. first bit line means; c. means for establishing in said first bit line means a logic state opposite to the logic state of an addressed memory element; d. second bit line means; e. inverter means connected between said first and second bit line means to establish in said second bit line means a logic state equal to the logic state of said addressed memory element; and f. means for establishing in said memory element the logic state of said second bit line means.
Claim 7
Dependent Claim
30 words
The array of claim 4, in which the establishment of said opposite logic state in said first bit line means does not affect the logic state of said memory element.
Claim 8
Dependent Claim
16 words
The array of claim 4, in which all of said logic state establishing means are ratioless.
Claim 9
Dependent Claim
32 words
The array of claim 4, further comprising writing means arranged to selectively disable said inverter means and establish in said second bit line means the logic state of externally supplied input data.
Claim 10
Dependent Claim
139 words
A random-access memory array, comprising: a. a plurality of individually addressable memory cells; b. bit line means; c. means for establishing in said bit line means a logic state indicativE of the logic state of an addressed memory cell; d. output circuit means including output gate means; e. prebias means arranged to maintain said output gate means in a first logic state but at a potential just sufficient to prevent its switching to the opposite logic state; f. means for disabling said prebias means during a predetermined portion of the operational cycle of said array; and g. buffer means responsive to the logic state in said but line for biasing said output gate means into said opposite logic state during said predetermined portion of said operational cycle upon the presence of a predetermined logic state in said bit line.
Claim 11
Dependent Claim
139 words
A random-access memory array, comprising: a. a plurality of individually addressable memory cells; b. bit line means; c. means for establishing in said bit line means a logic state indicativE of the logic state of an addressed memory cell; d. output circuit means including output gate means; e. prebias means arranged to maintain said output gate means in a first logic state but at a potential just sufficient to prevent its switching to the opposite logic state; f. means for disabling said prebias means during a predetermined portion of the operational cycle of said array; and g. buffer means responsive to the logic state in said but line for biasing said output gate means into said opposite logic state during said predetermined portion of said operational cycle upon the presence of a predetermined logic state in said bit line.
Claim 12
Dependent Claim
26 words
The array of claim 8, in which said predetermined bit line logic state is the same as said first logic state of said output gate means.
Claim 13
Dependent Claim
54 words
The array of claim 8, further comprising precharge means for precharging said buffer means into a predetermined logic state during a first portion of the operation cycle of said array, and address gate means for rendering said buffer means responsive to said bit line logic state during a second portion of said operational cycle.
Claim 14
Dependent Claim
47 words
The array of claim 10, further comprising capacitive means connected between said but line means and said address gating means so as to increase, during said second portion of said operational cycle, the bit line logic potential available to change the logic state of said buffer means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-17 | 1975-07-19 | 1976-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-17 | 1979-07-19 | 1980-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-17 | 1983-07-19 | 1984-01-18 | $7700.00 | Window Closed / Lapsed |