US3757308A
Expired / Lapsed
US
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Data processor
Assignee: Texas Instruments Inc
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Filing: 1971-09-03
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Granted: 1973-09-04
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Expires: 1991-09-03
Abstract
Abstract A MOS data processor fabricated on a single MOS semiconductor chip. The logic, arithmetic and storage functions are fabricated on one semiconductor chip.
Inventors
- 👤 R Fosdick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:56
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; G06F5/00; G06F5/01; G06F5/015; G06F7/57; G06F7/575
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
107 words
An MOS data processor fabricated on a single semiconductor chip comprising: an adder circuit included in said MOS data processor, each stage having a plurality of outputs, said adder circuit having a plurality of stages, and a carry circuit in each stage Of said adder, each carry circuit including first, second and third MOS transistors, the first transistor responsive to an adder output for generating a zero carry, the second transistor responsive to an adder output for generating a one carry, and the third transistor responsive to an adder output for propagating either a one carry or a zero carry to one of said plurality of stages.
Claim 2
Dependent Claim
107 words
An MOS data processor fabricated on a single semiconductor chip comprising: an adder circuit included in said MOS data processor, each stage having a plurality of outputs, said adder circuit having a plurality of stages, and a carry circuit in each stage Of said adder, each carry circuit including first, second and third MOS transistors, the first transistor responsive to an adder output for generating a zero carry, the second transistor responsive to an adder output for generating a one carry, and the third transistor responsive to an adder output for propagating either a one carry or a zero carry to one of said plurality of stages.
Claim 3
Dependent Claim
36 words
The MOS data processor claimed in claim 1 in which a carry input and a carry output are provided for each stage, and the third transistor is in series with the carry input and carry output.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-03 | 1977-03-05 | 1977-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-03 | 1981-03-05 | 1981-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-03 | 1985-03-05 | 1985-09-04 | $7700.00 | Window Closed / Lapsed |