Patent US2258179A successfully refreshed from Google Patents.
US3879712A
Expired / Lapsed
US
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Data processing system fault diagnostic arrangements
Assignee: BAE Systems Defence Systems Ltd
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Filing: 1973-05-31
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Granted: 1975-04-22
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Expires: 1993-05-31
Abstract
Abstract The invention provides arrangements for diagnosing faulty equipment using background job diagnostic software running in the on-line PP250 system. Each processor is provided with a diagnostic interface which is connectable to a processor-store bus, either directly or by way of a multiplexor, and which is addressable as part of the PP250 memory complex. Each diagnostic interface provides facilities for (i) forcing data patterns into the microbits and the data area (highway HO), (ii) monitoring important points in the processor equipment such as highway HO, the data-out register, the microbits and (iii) various basic functions relative to the stopping of the micro-program. The diagnostic interface printed circuit boards are normally removed and inserted only when a processor is to be diagnostically exercised.
Inventors
- 👤 Gordon Edge
- 👤 George Worthington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:16
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/267; G06F11/273; G06F11/2736
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
216 words
A digital data processing system comprising in combination: a plurality of processor modules; a plurality of data communication paths, one for each processor module allocated on a mutually exclusive basis and arranged to carry processor module generated address information; a plurality of multi-port access units each including a data communication path selection and termination means and an identity address recognition means conditioned with a unique identity code and responsive to said unique identity code within said address information when applied to any one of said data communication paths; a plurality of addressable memory modules each having a unique identity and incorporating one of said access unit; a group of addressable peripheral equipments each having a unique identity and incorporating one of said access units and a plurality of diagnostic interface units one for each processor module and each having a unique identity and incorporAting one of said access units and including an address decoder and a plurality of address-decoder selectable monitor, control and data injection points internal to the processing equipment of the said processor module and said address decoder is responsive to part of said address information accompanying the unique identity code particular to a diagnostic interface, a processor module having a fault being diagnosed by another processor module of said digital data processing system.
Claim 2
Dependent Claim
216 words
A digital data processing system comprising in combination: a plurality of processor modules; a plurality of data communication paths, one for each processor module allocated on a mutually exclusive basis and arranged to carry processor module generated address information; a plurality of multi-port access units each including a data communication path selection and termination means and an identity address recognition means conditioned with a unique identity code and responsive to said unique identity code within said address information when applied to any one of said data communication paths; a plurality of addressable memory modules each having a unique identity and incorporating one of said access unit; a group of addressable peripheral equipments each having a unique identity and incorporating one of said access units and a plurality of diagnostic interface units one for each processor module and each having a unique identity and incorporAting one of said access units and including an address decoder and a plurality of address-decoder selectable monitor, control and data injection points internal to the processing equipment of the said processor module and said address decoder is responsive to part of said address information accompanying the unique identity code particular to a diagnostic interface, a processor module having a fault being diagnosed by another processor module of said digital data processing system.
Claim 3
Dependent Claim
216 words
A digital data processing system comprising in combination: a plurality of processor modules; a plurality of data communication paths, one for each processor module allocated on a mutually exclusive basis and arranged to carry processor module generated address information; a plurality of multi-port access units each including a data communication path selection and termination means and an identity address recognition means conditioned with a unique identity code and responsive to said unique identity code within said address information when applied to any one of said data communication paths; a plurality of addressable memory modules each having a unique identity and incorporating one of said access unit; a group of addressable peripheral equipments each having a unique identity and incorporating one of said access units and a plurality of diagnostic interface units one for each processor module and each having a unique identity and incorporAting one of said access units and including an address decoder and a plurality of address-decoder selectable monitor, control and data injection points internal to the processing equipment of the said processor module and said address decoder is responsive to part of said address information accompanying the unique identity code particular to a diagnostic interface, a processor module having a fault being diagnosed by another processor module of said digital data processing system.
Claim 4
Dependent Claim
216 words
A digital data processing system comprising in combination: a plurality of processor modules; a plurality of data communication paths, one for each processor module allocated on a mutually exclusive basis and arranged to carry processor module generated address information; a plurality of multi-port access units each including a data communication path selection and termination means and an identity address recognition means conditioned with a unique identity code and responsive to said unique identity code within said address information when applied to any one of said data communication paths; a plurality of addressable memory modules each having a unique identity and incorporating one of said access unit; a group of addressable peripheral equipments each having a unique identity and incorporating one of said access units and a plurality of diagnostic interface units one for each processor module and each having a unique identity and incorporAting one of said access units and including an address decoder and a plurality of address-decoder selectable monitor, control and data injection points internal to the processing equipment of the said processor module and said address decoder is responsive to part of said address information accompanying the unique identity code particular to a diagnostic interface, a processor module having a fault being diagnosed by another processor module of said digital data processing system.
Claim 5
Dependent Claim
51 words
A digital-data processing system according to claim 1 wherein each said diagnostic interface unit includes a plurality of address-decoder selectable registers into which processor module generated control and data injecting information is written by applying to a data communication path said information accompanied by diagnostic interface and register identity address information.
Claim 6
Dependent Claim
48 words
A digital data processing system according to claim 2 wherein each said diagnostic interface unit includes a plurality of address-decoder selectable monitor points from which monitor information is read by an interrogating processor module by applying to a data communication path diagnostic interface and register identity address information.
Claim 7
Dependent Claim
43 words
A digital data processing system according to claim 3 wherein said processor equipment includes a clock control device and said diagnostic interface unit includes a clock control logic device and one of said control registers controls the functioning of said clock control logic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-21 | 1978-10-21 | 1979-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-21 | 1982-10-21 | 1983-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-21 | 1986-10-21 | 1987-04-22 | $7700.00 | Window Closed / Lapsed |