US3688263A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for diagnosing operation of a digital processor
Assignee: Unisys Corp
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Filing: 1971-04-19
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Granted: 1972-08-29
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Expires: 1991-04-19
Abstract
Abstract There is described a digital processor which, in response to a unique instruction, may be interrupted at any point in the fetch or execution of the next instruction and the contents of all the control flip-flops and registers can then be stored in a predetermined location in memory, following which the processor branches to a diagnostic routine.
Inventors
- 👤 Edward Balogh Jr
- 👤 Daewen J Cook
- 👤 Carl E Bube
- 👤 Robert V Airhart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0766
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
147 words
In a digital data processor in which machine stored instructions are fetched from a memory and executed, apparatus for testing the operation of the processor comprising a clock source, a memory, register means for storing an instruction, means for fetching an instruction from memory into said register means, means responsive to an instruction stored in said register for advancing the processor through a plurality of states in synchronism with said clock source to execute the instruction, means responsive to a predetermined instruction in the register means for storing information identifying a particular state of the processor, comparing means for comparing the plurality of states of the processor in fetching and executing a subsequent instruction with the state stored in said information storing means, and means responsive to the comparing means for interrupting the processor when it is in the particular state indicated by said information storing means.
Claim 2
Dependent Claim
147 words
In a digital data processor in which machine stored instructions are fetched from a memory and executed, apparatus for testing the operation of the processor comprising a clock source, a memory, register means for storing an instruction, means for fetching an instruction from memory into said register means, means responsive to an instruction stored in said register for advancing the processor through a plurality of states in synchronism with said clock source to execute the instruction, means responsive to a predetermined instruction in the register means for storing information identifying a particular state of the processor, comparing means for comparing the plurality of states of the processor in fetching and executing a subsequent instruction with the state stored in said information storing means, and means responsive to the comparing means for interrupting the processor when it is in the particular state indicated by said information storing means.
Claim 3
Dependent Claim
69 words
Apparatus as defined in claim 1 further including means responsive to said predetermined instruction in said register for storing information identifying a count condition, counting means responsive to said comparing means for counting each time the processor is set to said particular state, said processor interrupting means including means for interrupting the processor only when the counting means is counted a number of times corresponding to said count condition.
Claim 4
Dependent Claim
30 words
Apparatus as defined in claim 1 further including means responsive to said interrupting means for storing the contents of selected registers in the processor in a predetermined location in memory.
Claim 5
Dependent Claim
30 words
Apparatus as defined in claim 2 further including means responsive to said interrupting means for storing the contents of selected registers in the processor in a predetermined location in memory.
Claim 6
Dependent Claim
145 words
In a data processor in which a sequence of coded instructions are executed one at a time by advancing the processor through a sequence of logical states determined by the particular instruction being executed, apparatus for interrupting the operation of the processor at any selected logical state comprising means storing coded information identifying a preselected state of the processor, means responsive to a particular instruction when executed for loading the storing means with coded information identified by the instruction, control means set by said particular instruction for initiating a comparison between the state identified by the coded information in said storing means and each subsequent logical state of the processor, and means responsive to the control means for interrupting the normal operation of the processor when the processor is in the state corresponding to the state identified by said coded information in the storing means.
Claim 7
Dependent Claim
145 words
In a data processor in which a sequence of coded instructions are executed one at a time by advancing the processor through a sequence of logical states determined by the particular instruction being executed, apparatus for interrupting the operation of the processor at any selected logical state comprising means storing coded information identifying a preselected state of the processor, means responsive to a particular instruction when executed for loading the storing means with coded information identified by the instruction, control means set by said particular instruction for initiating a comparison between the state identified by the coded information in said storing means and each subsequent logical state of the processor, and means responsive to the control means for interrupting the normal operation of the processor when the processor is in the state corresponding to the state identified by said coded information in the storing means.
References Cited (Backward Citations)
US3343141A
Cited
US3405258A
Cited
US3363236A
Cited
US3585608A
Cited
US3576541A
Cited
US3548177A
Cited
US3518413A
Cited
US3536902A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-29 | 1976-02-28 | 1976-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-29 | 1980-02-28 | 1980-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-29 | 1984-02-28 | 1984-08-29 | $7700.00 | Window Closed / Lapsed |